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| author | Iru Cai <mytbk920423@gmail.com> | 2019-04-02 14:54:12 +0800 |
|---|---|---|
| committer | Iru Cai <mytbk920423@gmail.com> | 2019-04-02 14:54:12 +0800 |
| commit | 03ba6805c09ec86e597f12d25f33d705176f3aad (patch) | |
| tree | c38d7602f7683dc12e6234a6dd85f227f7250c3a /src/cpu | |
| parent | a1ca6275a05e504a2f8cf9a1b61768da126b266b (diff) | |
| download | gem5-03ba6805c09ec86e597f12d25f33d705176f3aad.tar.xz | |
print load inst
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/o3/rename_impl.hh | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh index 0f7839462..49eae9bb1 100644 --- a/src/cpu/o3/rename_impl.hh +++ b/src/cpu/o3/rename_impl.hh @@ -619,6 +619,7 @@ DefaultRename<Impl>::renameInsts(ThreadID tid) incrFullStat(source); break; } + DPRINTF(Rename, "[tid:%u]: load inst @ %s\n", tid, inst->pcState()); } if (inst->isStore()) { |