Add a very poor implementation of dealing with retries on timing requests. It is especially slow with tracing on since

it ends up being O(N^2). But it's probably going to have to change for the real bus anyway, so it should be rewritten then
Change recvRetry() to not accept a packet. Sendtiming should be called again (and can respond with false or true)
Removed Port Blocked/Unblocked and replaced with sendRetry().
Remove possibility of packet mangling if packet is going to be refused anyway in bridge

src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
    Change recvRetry() to not accept a packet. Sendtiming should be called again (and can respond with false or true)
src/dev/io_device.cc:
src/dev/io_device.hh:
    Make DMA Timing requests/responses work.
    Change recvRetry() to not accept a packet. Sendtiming should be called again (and can respond with false or true)
src/mem/bridge.cc:
src/mem/bridge.hh:
    Change recvRetry() to not accept a packet. Sendtiming should be called again (and can respond with false or true)
    Removed Port Blocked/Unblocked and replaced with sendRetry().
    Remove posibility of packet mangling if packet is going to be refused anyway.
src/mem/bus.cc:
src/mem/bus.hh:
    Add a very poor implementation of dealing with retries on timing requests. It is especially slow with tracing on since
    it ends up being O(N^2). But it's probably going to have to change for the real bus anyway, so it should be rewritten then
src/mem/port.hh:
    Change recvRetry() to not accept a packet. Sendtiming should be called again (and can respond with false or true)
    Removed Blocked/Unblocked port status, their functionality is really duplicated in the recvRetry() method

--HG--
extra : convert_revision : fab613404be54bfa7a4c67572bae7b559169e573

4 files changed, 14 insertions, 13 deletions

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 3cad6e43f..a0d26a8ab 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -106,11 +106,10 @@ AtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
     panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
 }
 
-Packet *
+void
 AtomicSimpleCPU::CpuPort::recvRetry()
 {
     panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
-    return NULL;
 }
 
 
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index ab3a3e8ef..65269bd6d 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -98,7 +98,7 @@ class AtomicSimpleCPU : public BaseSimpleCPU
 
         virtual void recvStatusChange(Status status);
 
-        virtual Packet *recvRetry();
+        virtual void recvRetry();
 
         virtual void getDeviceAddressRanges(AddrRangeList &resp,
             AddrRangeList &snoop)
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 7cdcdafa1..5f094d033 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -419,17 +419,18 @@ TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
     return true;
 }
 
-Packet *
+void
 TimingSimpleCPU::IcachePort::recvRetry()
 {
     // we shouldn't get a retry unless we have a packet that we're
     // waiting to transmit
     assert(cpu->ifetch_pkt != NULL);
     assert(cpu->_status == IcacheRetry);
-    cpu->_status = IcacheWaitResponse;
     Packet *tmp = cpu->ifetch_pkt;
-    cpu->ifetch_pkt = NULL;
-    return tmp;
+    if (sendTiming(tmp)) {
+        cpu->_status = IcacheWaitResponse;
+        cpu->ifetch_pkt = NULL;
+    }
 }
 
 void
@@ -459,17 +460,18 @@ TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt)
     return true;
 }
 
-Packet *
+void
 TimingSimpleCPU::DcachePort::recvRetry()
 {
     // we shouldn't get a retry unless we have a packet that we're
     // waiting to transmit
     assert(cpu->dcache_pkt != NULL);
     assert(cpu->_status == DcacheRetry);
-    cpu->_status = DcacheWaitResponse;
     Packet *tmp = cpu->dcache_pkt;
-    cpu->dcache_pkt = NULL;
-    return tmp;
+    if (sendTiming(tmp)) {
+        cpu->_status = DcacheWaitResponse;
+        cpu->dcache_pkt = NULL;
+    }
 }
 
 
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index b46631d5a..cb37824bc 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -100,7 +100,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
 
         virtual bool recvTiming(Packet *pkt);
 
-        virtual Packet *recvRetry();
+        virtual void recvRetry();
     };
 
     class DcachePort : public CpuPort
@@ -115,7 +115,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
 
         virtual bool recvTiming(Packet *pkt);
 
-        virtual Packet *recvRetry();
+        virtual void recvRetry();
     };
 
     IcachePort icachePort;