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| author | Gabe Black <gblack@eecs.umich.edu> | 2011-02-01 18:28:41 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2011-02-01 18:28:41 -0800 |
| commit | 119f5f8e94e673b1495dccce03b54773dc18afea (patch) | |
| tree | ff11fb58d39d12bd7c4fa5d94f629d718fe4e2ec /src/cpu | |
| parent | 4b4cd0303ea0e3b23e641933dbf0da57d1483764 (diff) | |
| download | gem5-119f5f8e94e673b1495dccce03b54773dc18afea.tar.xz | |
X86: Add L1 caches for the TLB walkers.
Small L1 caches are connected to the TLB walkers when caches are used. This
allows them to participate in the coherence protocol properly.
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/BaseCPU.py | 16 | ||||
| -rw-r--r-- | src/cpu/o3/O3CPU.py | 4 |
2 files changed, 13 insertions, 7 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 868f47015..0669a7de4 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -166,7 +166,7 @@ class BaseCPU(MemObject): if p != 'physmem_port': exec('self.%s = bus.port' % p) - def addPrivateSplitL1Caches(self, ic, dc): + def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): assert(len(self._mem_ports) < 8) self.icache = ic self.dcache = dc @@ -174,13 +174,19 @@ class BaseCPU(MemObject): self.dcache_port = dc.cpu_side self._mem_ports = ['icache.mem_side', 'dcache.mem_side'] if buildEnv['FULL_SYSTEM']: - if buildEnv['TARGET_ISA'] in ['x86', 'arm']: - self._mem_ports += ["itb.walker.port", "dtb.walker.port"] if buildEnv['TARGET_ISA'] == 'x86': + self.itb_walker_cache = iwc + self.dtb_walker_cache = dwc + self.itb.walker.port = iwc.cpu_side + self.dtb.walker.port = dwc.cpu_side + self._mem_ports += ["itb_walker_cache.mem_side", \ + "dtb_walker_cache.mem_side"] self._mem_ports += ["interrupts.pio", "interrupts.int_port"] + elif buildEnv['TARGET_ISA'] == 'arm': + self._mem_ports += ["itb.walker.port", "dtb.walker.port"] - def addTwoLevelCacheHierarchy(self, ic, dc, l2c): - self.addPrivateSplitL1Caches(ic, dc) + def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): + self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) self.toL2Bus = Bus() self.connectMemPorts(self.toL2Bus) self.l2cache = l2c diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py index 3f2210e44..38fee369c 100644 --- a/src/cpu/o3/O3CPU.py +++ b/src/cpu/o3/O3CPU.py @@ -141,7 +141,7 @@ class DerivO3CPU(BaseCPU): smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy") - def addPrivateSplitL1Caches(self, ic, dc): - BaseCPU.addPrivateSplitL1Caches(self, ic, dc) + def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): + BaseCPU.addPrivateSplitL1Caches(self, ic, dc, iwc, dwc) self.icache.tgts_per_mshr = 20 self.dcache.tgts_per_mshr = 20 |