arch: ISA parser additions of vector registers

Reiley's update :) of the isa parser definitions. My addition of the
vector element operand concept for the ISA parser. Nathanael's modification
creating a hierarchy between vector registers and its constituencies to the
isa parser.

Some fixes/updates on top to consider instructions as vectors instead of
floating when they use the VectorRF. Some counters added to all the
models to keep faithful counts.

Change-Id: Id8f162a525240dfd7ba884c5a4d9fa69f4050101
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2706
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

9 files changed, 85 insertions, 9 deletions

diff --git a/src/cpu/StaticInstFlags.py b/src/cpu/StaticInstFlags.py
index ef29726fc..55ef456ce 100644
--- a/src/cpu/StaticInstFlags.py
+++ b/src/cpu/StaticInstFlags.py
@@ -58,6 +58,8 @@ class StaticInstFlags(Enum):
         'IsInteger',        # References integer regs.
         'IsFloating',       # References FP regs.
         'IsCC',             # References CC regs.
+        'IsVector',         # References Vector regs.
+        'IsVectorElem',     # References Vector reg elems.
 
         'IsMemRef',         # References memory (load, store, or prefetch)
         'IsLoad',           # Reads from memory (load or prefetch).
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 132c390b3..d7d32e629 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -517,6 +517,7 @@ class BaseDynInst : public ExecContext, public RefCounted
     bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
     bool isInteger()      const { return staticInst->isInteger(); }
     bool isFloating()     const { return staticInst->isFloating(); }
+    bool isVector()       const { return staticInst->isVector(); }
     bool isControl()      const { return staticInst->isControl(); }
     bool isCall()         const { return staticInst->isCall(); }
     bool isReturn()       const { return staticInst->isReturn(); }
diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index 3cce7f69c..5977f94f3 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -517,6 +517,8 @@ class DefaultCommit
     Stats::Vector statComMembars;
     /** Total number of committed branches. */
     Stats::Vector statComBranches;
+    /** Total number of vector instructions */
+    Stats::Vector statComVector;
     /** Total number of floating point instructions */
     Stats::Vector statComFloating;
     /** Total number of integer instructions */
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index ea77f18fb..aba2696c2 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -260,6 +260,13 @@ DefaultCommit<Impl>::regStats()
         .flags(total)
         ;
 
+    statComVector
+        .init(cpu->numThreads)
+        .name(name() + ".vec_insts")
+        .desc("Number of committed Vector instructions.")
+        .flags(total)
+        ;
+
     statComInteger
         .init(cpu->numThreads)
         .name(name()+".int_insts")
@@ -1404,6 +1411,9 @@ DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
     // Floating Point Instruction
     if (inst->isFloating())
         statComFloating[tid]++;
+    // Vector Instruction
+    if (inst->isVector())
+        statComVector[tid]++;
 
     // Function Calls
     if (inst->isCall())
diff --git a/src/cpu/o3/inst_queue.hh b/src/cpu/o3/inst_queue.hh
index 23d8d416c..64f8aa1be 100644
--- a/src/cpu/o3/inst_queue.hh
+++ b/src/cpu/o3/inst_queue.hh
@@ -543,10 +543,14 @@ class InstructionQueue
     Stats::Scalar intInstQueueWakeupAccesses;
     Stats::Scalar fpInstQueueReads;
     Stats::Scalar fpInstQueueWrites;
-    Stats::Scalar fpInstQueueWakeupQccesses;
+    Stats::Scalar fpInstQueueWakeupAccesses;
+    Stats::Scalar vecInstQueueReads;
+    Stats::Scalar vecInstQueueWrites;
+    Stats::Scalar vecInstQueueWakeupAccesses;
 
     Stats::Scalar intAluAccesses;
     Stats::Scalar fpAluAccesses;
+    Stats::Scalar vecAluAccesses;
 };
 
 #endif //__CPU_O3_INST_QUEUE_HH__
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index 2b113ae04..3da72fd86 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -364,7 +364,7 @@ InstructionQueue<Impl>::regStats()
         .desc("Number of floating instruction queue writes")
         .flags(total);
 
-    fpInstQueueWakeupQccesses
+    fpInstQueueWakeupAccesses
         .name(name() + ".fp_inst_queue_wakeup_accesses")
         .desc("Number of floating instruction queue wakeup accesses")
         .flags(total);
@@ -567,7 +567,13 @@ template <class Impl>
 void
 InstructionQueue<Impl>::insert(DynInstPtr &new_inst)
 {
-    new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++;
+    if (new_inst->isFloating()) {
+        fpInstQueueWrites++;
+    } else if (new_inst->isVector()) {
+        vecInstQueueWrites++;
+    } else {
+        intInstQueueWrites++;
+    }
     // Make sure the instruction is valid
     assert(new_inst);
 
@@ -609,7 +615,13 @@ InstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst)
 {
     // @todo: Clean up this code; can do it by setting inst as unable
     // to issue, then calling normal insert on the inst.
-    new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++;
+    if (new_inst->isFloating()) {
+        fpInstQueueWrites++;
+    } else if (new_inst->isVector()) {
+        vecInstQueueWrites++;
+    } else {
+        intInstQueueWrites++;
+    }
 
     assert(new_inst);
 
@@ -660,8 +672,10 @@ InstructionQueue<Impl>::getInstToExecute()
     assert(!instsToExecute.empty());
     DynInstPtr inst = instsToExecute.front();
     instsToExecute.pop_front();
-    if (inst->isFloating()){
+    if (inst->isFloating()) {
         fpInstQueueReads++;
+    } else if (inst->isVector()) {
+        vecInstQueueReads++;
     } else {
         intInstQueueReads++;
     }
@@ -783,7 +797,13 @@ InstructionQueue<Impl>::scheduleReadyInsts()
 
         DynInstPtr issuing_inst = readyInsts[op_class].top();
 
-        issuing_inst->isFloating() ? fpInstQueueReads++ : intInstQueueReads++;
+        if (issuing_inst->isFloating()) {
+            fpInstQueueReads++;
+        } else if (issuing_inst->isVector()) {
+            vecInstQueueReads++;
+        } else {
+            intInstQueueReads++;
+        }
 
         assert(issuing_inst->seqNum == (*order_it).oldestInst);
 
@@ -810,7 +830,13 @@ InstructionQueue<Impl>::scheduleReadyInsts()
 
         if (op_class != No_OpClass) {
             idx = fuPool->getUnit(op_class);
-            issuing_inst->isFloating() ? fpAluAccesses++ : intAluAccesses++;
+            if (issuing_inst->isFloating()) {
+                fpAluAccesses++;
+            } else if (issuing_inst->isVector()) {
+                vecAluAccesses++;
+            } else {
+                intAluAccesses++;
+            }
             if (idx > FUPool::NoFreeFU) {
                 op_latency = fuPool->getOpLatency(op_class);
             }
@@ -955,7 +981,9 @@ InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst)
 
     // The instruction queue here takes care of both floating and int ops
     if (completed_inst->isFloating()) {
-        fpInstQueueWakeupQccesses++;
+        fpInstQueueWakeupAccesses++;
+    } else if (completed_inst->isVector()) {
+        vecInstQueueWakeupAccesses++;
     } else {
         intInstQueueWakeupAccesses++;
     }
@@ -1189,7 +1217,13 @@ InstructionQueue<Impl>::doSquash(ThreadID tid)
            (*squash_it)->seqNum > squashedSeqNum[tid]) {
 
         DynInstPtr squashed_inst = (*squash_it);
-        squashed_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++;
+        if (squashed_inst->isFloating()) {
+            fpInstQueueWrites++;
+        } else if (squashed_inst->isVector()) {
+            vecInstQueueWrites++;
+        } else {
+            intInstQueueWrites++;
+        }
 
         // Only handle the instruction if it actually is in the IQ and
         // hasn't already been squashed in the IQ.
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 57cea4ba7..783967602 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -252,6 +252,11 @@ BaseSimpleCPU::regStats()
             .desc("Number of float alu accesses")
             ;
 
+        t_info.numVecAluAccesses
+            .name(thread_str + ".num_vec_alu_accesses")
+            .desc("Number of vector alu accesses")
+            ;
+
         t_info.numCallsReturns
             .name(thread_str + ".num_func_calls")
             .desc("number of times a function call or return occured")
@@ -272,6 +277,11 @@ BaseSimpleCPU::regStats()
             .desc("number of float instructions")
             ;
 
+        t_info.numVecInsts
+            .name(thread_str + ".num_vec_insts")
+            .desc("number of vector instructions")
+            ;
+
         t_info.numIntRegReads
             .name(thread_str + ".num_int_register_reads")
             .desc("number of times the integer registers were read")
@@ -613,6 +623,12 @@ BaseSimpleCPU::postExecute()
         t_info.numFpInsts++;
     }
 
+    //vector alu accesses
+    if (curStaticInst->isVector()){
+        t_info.numVecAluAccesses++;
+        t_info.numVecInsts++;
+    }
+
     //number of function calls/returns to get window accesses
     if (curStaticInst->isCall() || curStaticInst->isReturn()){
         t_info.numCallsReturns++;
diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh
index 0f546407d..6d51e5ed9 100644
--- a/src/cpu/simple/exec_context.hh
+++ b/src/cpu/simple/exec_context.hh
@@ -94,6 +94,9 @@ class SimpleExecContext : public ExecContext {
     // Number of float alu accesses
     Stats::Scalar numFpAluAccesses;
 
+    // Number of vector alu accesses
+    Stats::Scalar numVecAluAccesses;
+
     // Number of function calls/returns
     Stats::Scalar numCallsReturns;
 
@@ -106,6 +109,9 @@ class SimpleExecContext : public ExecContext {
     // Number of float instructions
     Stats::Scalar numFpInsts;
 
+    // Number of vector instructions
+    Stats::Scalar numVecInsts;
+
     // Number of integer register file accesses
     Stats::Scalar numIntRegReads;
     Stats::Scalar numIntRegWrites;
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index e7507c6a6..883c532ac 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -150,6 +150,7 @@ class StaticInst : public RefCounted, public StaticInstFlags
 
     bool isInteger()      const { return flags[IsInteger]; }
     bool isFloating()     const { return flags[IsFloating]; }
+    bool isVector()       const { return flags[IsVector]; }
     bool isCC()           const { return flags[IsCC]; }
 
     bool isControl()      const { return flags[IsControl]; }