cpu: rename *_DepTag constants to *_Reg_Base

Make these names more meaningful.

Specifically, made these substitutions:

s/FP_Base_DepTag/FP_Reg_Base/g;
s/Ctrl_Base_DepTag/Misc_Reg_Base/g;
s/Max_DepTag/Max_Reg_Index/g;

8 files changed, 38 insertions, 38 deletions

diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 19d3420ec..637481706 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -213,13 +213,13 @@ class CheckerCPU : public BaseCPU
 
     FloatReg readFloatRegOperand(const StaticInst *si, int idx)
     {
-        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
+        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
         return thread->readFloatReg(reg_idx);
     }
 
     FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
     {
-        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
+        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
         return thread->readFloatRegBits(reg_idx);
     }
 
@@ -239,7 +239,7 @@ class CheckerCPU : public BaseCPU
 
     void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
     {
-        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
+        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
         thread->setFloatReg(reg_idx, val);
         setResult<double>(val);
     }
@@ -247,7 +247,7 @@ class CheckerCPU : public BaseCPU
     void setFloatRegOperandBits(const StaticInst *si, int idx,
                                 FloatRegBits val)
     {
-        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
+        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
         thread->setFloatRegBits(reg_idx, val);
         setResult<uint64_t>(val);
     }
@@ -294,14 +294,14 @@ class CheckerCPU : public BaseCPU
 
     MiscReg readMiscRegOperand(const StaticInst *si, int idx)
     {
-        int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
+        int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base;
         return thread->readMiscReg(reg_idx);
     }
 
     void setMiscRegOperand(
             const StaticInst *si, int idx, const MiscReg &val)
     {
-        int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
+        int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
         return thread->setMiscReg(reg_idx, val);
     }
 
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 1967e02f3..185fed88e 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -607,7 +607,7 @@ Checker<Impl>::copyResult(DynInstPtr &inst, uint64_t mismatch_val,
             thread->setFloatRegBits(idx, mismatch_val);
             break;
           case MiscRegClass:
-            thread->setMiscReg(idx - TheISA::Ctrl_Base_DepTag,
+            thread->setMiscReg(idx - TheISA::Misc_Reg_Base,
                                mismatch_val);
             break;
         }
@@ -626,7 +626,7 @@ Checker<Impl>::copyResult(DynInstPtr &inst, uint64_t mismatch_val,
             break;
           case MiscRegClass:
             // Try to get the proper misc register index for ARM here...
-            thread->setMiscReg(idx - TheISA::Ctrl_Base_DepTag, res);
+            thread->setMiscReg(idx - TheISA::Misc_Reg_Base, res);
             break;
             // else Register is out of range...
         }
diff --git a/src/cpu/inorder/resources/use_def.cc b/src/cpu/inorder/resources/use_def.cc
index d7863095d..d25925b9b 100644
--- a/src/cpu/inorder/resources/use_def.cc
+++ b/src/cpu/inorder/resources/use_def.cc
@@ -247,7 +247,7 @@ UseDefUnit::execute(int slot_idx)
                         DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Reading Float Reg %i"
                                 " (%i) from Register File:%x (%08f).\n",
                                 tid, seq_num,
-                                reg_idx - FP_Base_DepTag, flat_idx,
+                                reg_idx - FP_Reg_Base, flat_idx,
                                 cpu->readFloatRegBits(flat_idx,
                                                       inst->readTid()),
                                 cpu->readFloatReg(flat_idx,
@@ -269,7 +269,7 @@ UseDefUnit::execute(int slot_idx)
                         DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Reading Misc Reg %i "
                                 " (%i) from Register File:0x%x.\n",
                                 tid, seq_num,
-                                reg_idx - Ctrl_Base_DepTag, flat_idx,
+                                reg_idx - Misc_Reg_Base, flat_idx,
                                 cpu->readMiscReg(flat_idx,
                                 inst->readTid()));
                         inst->setIntSrc(ud_idx,
@@ -315,7 +315,7 @@ UseDefUnit::execute(int slot_idx)
                             DPRINTF(InOrderUseDef, "[tid:%i]: Forwarding dest."
                                     " reg %i (%i) value 0x%x from "
                                     "[sn:%i] to [sn:%i] source #%i.\n",
-                                    tid, reg_idx - FP_Base_DepTag, flat_idx,
+                                    tid, reg_idx - FP_Reg_Base, flat_idx,
                                     forward_inst->readFloatResult(dest_reg_idx),
                                     forward_inst->seqNum, inst->seqNum, ud_idx);
                             inst->setFloatSrc(ud_idx,
@@ -329,7 +329,7 @@ UseDefUnit::execute(int slot_idx)
                             DPRINTF(InOrderUseDef, "[tid:%i]: Forwarding dest."
                                     " reg %i (%i) value 0x%x from "
                                     "[sn:%i] to [sn:%i] source #%i.\n",
-                                    tid, reg_idx - Ctrl_Base_DepTag, flat_idx,
+                                    tid, reg_idx - Misc_Reg_Base, flat_idx,
                                     forward_inst->readIntResult(dest_reg_idx),
                                     forward_inst->seqNum, 
                                     inst->seqNum, ud_idx);
@@ -412,7 +412,7 @@ UseDefUnit::execute(int slot_idx)
                                     tid, seq_num,
                                     inst->readFloatResult(ud_idx), 
                                     inst->readFloatBitsResult(ud_idx),
-                                    reg_idx - FP_Base_DepTag, flat_idx);
+                                    reg_idx - FP_Reg_Base, flat_idx);
 
                             // Check for FloatRegBits Here
                             cpu->setFloatRegBits(flat_idx,
@@ -425,7 +425,7 @@ UseDefUnit::execute(int slot_idx)
                                     "idx %i (%i).\n",
                                     tid, seq_num, inst->readFloatResult(ud_idx),
                                     inst->readIntResult(ud_idx), 
-                                    reg_idx - FP_Base_DepTag, flat_idx);
+                                    reg_idx - FP_Reg_Base, flat_idx);
 
                             cpu->setFloatReg(flat_idx,
                                              inst->readFloatResult(ud_idx),
@@ -438,7 +438,7 @@ UseDefUnit::execute(int slot_idx)
                                     tid, seq_num,
                                     inst->readFloatResult(ud_idx), 
                                     inst->readIntResult(ud_idx), 
-                                    reg_idx - FP_Base_DepTag, flat_idx);
+                                    reg_idx - FP_Reg_Base, flat_idx);
 
                             cpu->setFloatReg(flat_idx,
                                              inst->readFloatResult(ud_idx),
@@ -458,7 +458,7 @@ UseDefUnit::execute(int slot_idx)
 
                         DPRINTF(InOrderUseDef, "[tid:%i]: Writing Misc. 0x%x "
                                 "to register idx %i.\n",
-                                tid, inst->readIntResult(ud_idx), reg_idx - Ctrl_Base_DepTag);
+                                tid, inst->readIntResult(ud_idx), reg_idx - Misc_Reg_Base);
 
                         // Remove Dependencies
                         regDepMap[tid]->removeFront(reg_type, flat_idx, inst);
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index ece42b81a..15a82851b 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -175,7 +175,7 @@ class BaseO3DynInst : public BaseDynInst<Impl>
     TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
     {
         return this->cpu->readMiscReg(
-                si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
+                si->srcRegIdx(idx) - TheISA::Misc_Reg_Base,
                 this->threadNumber);
     }
 
@@ -185,7 +185,7 @@ class BaseO3DynInst : public BaseDynInst<Impl>
     void setMiscRegOperand(const StaticInst *si, int idx,
                                      const MiscReg &val)
     {
-        int misc_reg = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
+        int misc_reg = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
         setMiscReg(misc_reg, val);
     }
 
diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index 3ab0afe11..60a929551 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -953,7 +953,7 @@ DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid)
             break;
 
           case FloatRegClass:
-            src_reg = src_reg - TheISA::FP_Base_DepTag;
+            src_reg = src_reg - TheISA::FP_Reg_Base;
             flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg);
             DPRINTF(Rename, "Flattening index %d to %d.\n",
                     (int)src_reg, (int)flat_src_reg);
@@ -961,7 +961,7 @@ DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid)
             break;
 
           case MiscRegClass:
-            flat_src_reg = src_reg - TheISA::Ctrl_Base_DepTag +
+            flat_src_reg = src_reg - TheISA::Misc_Reg_Base +
                            TheISA::NumFloatRegs + TheISA::NumIntRegs;
             DPRINTF(Rename, "Adjusting reg index from %d to %d.\n",
                     src_reg, flat_src_reg);
@@ -1018,7 +1018,7 @@ DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid)
             break;
 
           case FloatRegClass:
-            dest_reg = dest_reg - TheISA::FP_Base_DepTag;
+            dest_reg = dest_reg - TheISA::FP_Reg_Base;
             flat_dest_reg = inst->tcBase()->flattenFloatIndex(dest_reg);
             DPRINTF(Rename, "Flattening index %d to %d.\n",
                     (int)dest_reg, (int)flat_dest_reg);
@@ -1028,7 +1028,7 @@ DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid)
           case MiscRegClass:
             // Floating point and Miscellaneous registers need their indexes
             // adjusted to account for the expanded number of flattened int regs.
-            flat_dest_reg = dest_reg - TheISA::Ctrl_Base_DepTag +
+            flat_dest_reg = dest_reg - TheISA::Misc_Reg_Base +
                             TheISA::NumIntRegs + TheISA::NumFloatRegs;
             DPRINTF(Rename, "Adjusting reg index from %d to %d.\n",
                     dest_reg, flat_dest_reg);
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index f64f287ea..fcab901cf 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -458,7 +458,7 @@ OzoneCPU<Impl>::tick()
 
     _status = Running;
     thread.renameTable[ZeroReg]->setIntResult(0);
-    thread.renameTable[ZeroReg+TheISA::FP_Base_DepTag]->
+    thread.renameTable[ZeroReg+TheISA::FP_Reg_Base]->
         setDoubleResult(0.0);
 
     comm.advance();
@@ -727,7 +727,7 @@ OzoneCPU<Impl>::OzoneTC::copyArchRegs(ThreadContext *tc)
 
     // Then loop through the floating point registers.
     for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
-        int fp_idx = i + TheISA::FP_Base_DepTag;
+        int fp_idx = i + TheISA::FP_Reg_Base;
         thread->renameTable[fp_idx]->setIntResult(tc->readFloatRegBits(i));
     }
 
@@ -756,7 +756,7 @@ template <class Impl>
 double
 OzoneCPU<Impl>::OzoneTC::readFloatReg(int reg_idx)
 {
-    int idx = reg_idx + TheISA::FP_Base_DepTag;
+    int idx = reg_idx + TheISA::FP_Reg_Base;
     return thread->renameTable[idx]->readFloatResult();
 }
 
@@ -764,7 +764,7 @@ template <class Impl>
 uint64_t
 OzoneCPU<Impl>::OzoneTC::readFloatRegBits(int reg_idx)
 {
-    int idx = reg_idx + TheISA::FP_Base_DepTag;
+    int idx = reg_idx + TheISA::FP_Reg_Base;
     return thread->renameTable[idx]->readIntResult();
 }
 
@@ -783,7 +783,7 @@ template <class Impl>
 void
 OzoneCPU<Impl>::OzoneTC::setFloatReg(int reg_idx, FloatReg val)
 {
-    int idx = reg_idx + TheISA::FP_Base_DepTag;
+    int idx = reg_idx + TheISA::FP_Reg_Base;
 
     thread->renameTable[idx]->setDoubleResult(val);
 
diff --git a/src/cpu/reg_class.hh b/src/cpu/reg_class.hh
index e96c94cbb..c9d4b1c4f 100644
--- a/src/cpu/reg_class.hh
+++ b/src/cpu/reg_class.hh
@@ -65,19 +65,19 @@ inline
 RegClass regIdxToClass(TheISA::RegIndex reg_idx,
                        TheISA::RegIndex *rel_reg_idx = NULL)
 {
-    assert(reg_idx < TheISA::Max_DepTag);
+    assert(reg_idx < TheISA::Max_Reg_Index);
     RegClass cl;
     int offset;
 
-    if (reg_idx < TheISA::FP_Base_DepTag) {
+    if (reg_idx < TheISA::FP_Reg_Base) {
         cl = IntRegClass;
         offset = 0;
-    } else if (reg_idx < TheISA::Ctrl_Base_DepTag) {
+    } else if (reg_idx < TheISA::Misc_Reg_Base) {
         cl = FloatRegClass;
-        offset = TheISA::FP_Base_DepTag;
+        offset = TheISA::FP_Reg_Base;
     } else {
         cl = MiscRegClass;
-        offset = TheISA::Ctrl_Base_DepTag;
+        offset = TheISA::Misc_Reg_Base;
     }
 
     if (rel_reg_idx)
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 7e84dcc16..f2e1b278a 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -296,14 +296,14 @@ class BaseSimpleCPU : public BaseCPU
     FloatReg readFloatRegOperand(const StaticInst *si, int idx)
     {
         numFpRegReads++;
-        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
+        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
         return thread->readFloatReg(reg_idx);
     }
 
     FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
     {
         numFpRegReads++;
-        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
+        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
         return thread->readFloatRegBits(reg_idx);
     }
 
@@ -316,7 +316,7 @@ class BaseSimpleCPU : public BaseCPU
     void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
     {
         numFpRegWrites++;
-        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
+        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
         thread->setFloatReg(reg_idx, val);
     }
 
@@ -324,7 +324,7 @@ class BaseSimpleCPU : public BaseCPU
                                 FloatRegBits val)
     {
         numFpRegWrites++;
-        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
+        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
         thread->setFloatRegBits(reg_idx, val);
     }
 
@@ -362,7 +362,7 @@ class BaseSimpleCPU : public BaseCPU
     MiscReg readMiscRegOperand(const StaticInst *si, int idx)
     {
         numIntRegReads++;
-        int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
+        int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base;
         return thread->readMiscReg(reg_idx);
     }
 
@@ -370,7 +370,7 @@ class BaseSimpleCPU : public BaseCPU
             const StaticInst *si, int idx, const MiscReg &val)
     {
         numIntRegWrites++;
-        int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
+        int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
         return thread->setMiscReg(reg_idx, val);
     }