Registers: Get rid of the float register width parameter.

24 files changed, 50 insertions, 576 deletions

diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 3b378700e..450ce6228 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -211,25 +211,12 @@ class CheckerCPU : public BaseCPU
         return thread->readIntReg(si->srcRegIdx(idx));
     }
 
-    FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
-    {
-        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
-        return thread->readFloatReg(reg_idx, width);
-    }
-
     FloatReg readFloatRegOperand(const StaticInst *si, int idx)
     {
         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
         return thread->readFloatReg(reg_idx);
     }
 
-    FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
-                                         int width)
-    {
-        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
-        return thread->readFloatRegBits(reg_idx, width);
-    }
-
     FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
     {
         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
@@ -242,21 +229,6 @@ class CheckerCPU : public BaseCPU
         result.integer = val;
     }
 
-    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
-                            int width)
-    {
-        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
-        thread->setFloatReg(reg_idx, val, width);
-        switch(width) {
-          case 32:
-            result.dbl = (double)val;
-            break;
-          case 64:
-            result.dbl = val;
-            break;
-        };
-    }
-
     void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
     {
         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
@@ -265,14 +237,6 @@ class CheckerCPU : public BaseCPU
     }
 
     void setFloatRegOperandBits(const StaticInst *si, int idx,
-                                FloatRegBits val, int width)
-    {
-        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
-        thread->setFloatRegBits(reg_idx, val, width);
-        result.integer = val;
-    }
-
-    void setFloatRegOperandBits(const StaticInst *si, int idx,
                                 FloatRegBits val)
     {
         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index 2176c597a..d38bd2915 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -174,15 +174,9 @@ class CheckerThreadContext : public ThreadContext
     uint64_t readIntReg(int reg_idx)
     { return actualTC->readIntReg(reg_idx); }
 
-    FloatReg readFloatReg(int reg_idx, int width)
-    { return actualTC->readFloatReg(reg_idx, width); }
-
     FloatReg readFloatReg(int reg_idx)
     { return actualTC->readFloatReg(reg_idx); }
 
-    FloatRegBits readFloatRegBits(int reg_idx, int width)
-    { return actualTC->readFloatRegBits(reg_idx, width); }
-
     FloatRegBits readFloatRegBits(int reg_idx)
     { return actualTC->readFloatRegBits(reg_idx); }
 
@@ -192,24 +186,12 @@ class CheckerThreadContext : public ThreadContext
         checkerTC->setIntReg(reg_idx, val);
     }
 
-    void setFloatReg(int reg_idx, FloatReg val, int width)
-    {
-        actualTC->setFloatReg(reg_idx, val, width);
-        checkerTC->setFloatReg(reg_idx, val, width);
-    }
-
     void setFloatReg(int reg_idx, FloatReg val)
     {
         actualTC->setFloatReg(reg_idx, val);
         checkerTC->setFloatReg(reg_idx, val);
     }
 
-    void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
-    {
-        actualTC->setFloatRegBits(reg_idx, val, width);
-        checkerTC->setFloatRegBits(reg_idx, val, width);
-    }
-
     void setFloatRegBits(int reg_idx, FloatRegBits val)
     {
         actualTC->setFloatRegBits(reg_idx, val);
diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index 2b9fe4bcf..3d07e95f3 100644
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -50,17 +50,9 @@ class ExecContext {
     /** Reads an integer register. */
     uint64_t readIntRegOperand(const StaticInst *si, int idx);
 
-    /** Reads a floating point register of a specific width. */
-    FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width);
-
     /** Reads a floating point register of single register width. */
     FloatReg readFloatRegOperand(const StaticInst *si, int idx);
 
-    /** Reads a floating point register of a specific width in its
-     * binary format, instead of by value. */
-    FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
-                                         int width);
-
     /** Reads a floating point register in its binary format, instead
      * of by value. */
     FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx);
@@ -68,18 +60,9 @@ class ExecContext {
     /** Sets an integer register to a value. */
     void setIntRegOperand(const StaticInst *si, int idx, uint64_t val);
 
-    /** Sets a floating point register of a specific width to a value. */
-    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
-                            int width);
-
     /** Sets a floating point register of single width to a value. */
     void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val);
 
-    /** Sets the bits of a floating point register of a specific width
-     * to a binary value. */
-    void setFloatRegOperandBits(const StaticInst *si, int idx,
-                                FloatRegBits val, int width);
-
     /** Sets the bits of a floating point register of single width
      * to a binary value. */
     void setFloatRegOperandBits(const StaticInst *si, int idx,
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 51d62e179..fc8723829 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -890,16 +890,15 @@ InOrderCPU::readIntReg(int reg_idx, ThreadID tid)
 }
 
 FloatReg
-InOrderCPU::readFloatReg(int reg_idx, ThreadID tid, int width)
+InOrderCPU::readFloatReg(int reg_idx, ThreadID tid)
 {
-
-    return floatRegFile[tid].readReg(reg_idx, width);
+    return floatRegFile[tid].readReg(reg_idx);
 }
 
 FloatRegBits
-InOrderCPU::readFloatRegBits(int reg_idx, ThreadID tid, int width)
+InOrderCPU::readFloatRegBits(int reg_idx, ThreadID tid)
 {;
-    return floatRegFile[tid].readRegBits(reg_idx, width);
+    return floatRegFile[tid].readRegBits(reg_idx);
 }
 
 void
@@ -910,17 +909,16 @@ InOrderCPU::setIntReg(int reg_idx, uint64_t val, ThreadID tid)
 
 
 void
-InOrderCPU::setFloatReg(int reg_idx, FloatReg val, ThreadID tid, int width)
+InOrderCPU::setFloatReg(int reg_idx, FloatReg val, ThreadID tid)
 {
-    floatRegFile[tid].setReg(reg_idx, val, width);
+    floatRegFile[tid].setReg(reg_idx, val);
 }
 
 
 void
-InOrderCPU::setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid,
-                            int width)
+InOrderCPU::setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid)
 {
-    floatRegFile[tid].setRegBits(reg_idx, val, width);
+    floatRegFile[tid].setRegBits(reg_idx, val);
 }
 
 uint64_t
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index bfc5139cf..bda4c41bd 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -404,19 +404,15 @@ class InOrderCPU : public BaseCPU
     /** Register file accessors  */
     uint64_t readIntReg(int reg_idx, ThreadID tid);
 
-    FloatReg readFloatReg(int reg_idx, ThreadID tid,
-                          int width = TheISA::SingleWidth);
+    FloatReg readFloatReg(int reg_idx, ThreadID tid);
 
-    FloatRegBits readFloatRegBits(int reg_idx, ThreadID tid,
-                                  int width = TheISA::SingleWidth);
+    FloatRegBits readFloatRegBits(int reg_idx, ThreadID tid);
 
     void setIntReg(int reg_idx, uint64_t val, ThreadID tid);
 
-    void setFloatReg(int reg_idx, FloatReg val, ThreadID tid,
-                     int width = TheISA::SingleWidth);
+    void setFloatReg(int reg_idx, FloatReg val, ThreadID tid);
 
-    void setFloatRegBits(int reg_idx, FloatRegBits val,  ThreadID tid,
-                         int width = TheISA::SingleWidth);
+    void setFloatRegBits(int reg_idx, FloatRegBits val,  ThreadID tid);
 
     /** Reads a miscellaneous register. */
     MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
diff --git a/src/cpu/inorder/inorder_dyn_inst.cc b/src/cpu/inorder/inorder_dyn_inst.cc
index ee2e5500e..a6abb28b2 100644
--- a/src/cpu/inorder/inorder_dyn_inst.cc
+++ b/src/cpu/inorder/inorder_dyn_inst.cc
@@ -366,14 +366,9 @@ InOrderDynInst::setIntSrc(int idx, uint64_t val)
 
 /** Records an fp register being set to a value. */
 void
-InOrderDynInst::setFloatSrc(int idx, FloatReg val, int width)
+InOrderDynInst::setFloatSrc(int idx, FloatReg val)
 {
-    if (width == 32)
-        instSrc[idx].dbl = val;
-    else if (width == 64)
-        instSrc[idx].dbl = val;
-    else
-        panic("Unsupported width!");
+    instSrc[idx].dbl = val;
 }
 
 /** Records an fp register being set to an integer value. */
@@ -394,22 +389,15 @@ InOrderDynInst::readIntRegOperand(const StaticInst *si, int idx, ThreadID tid)
 
 /** Reads a FP register. */
 FloatReg
-InOrderDynInst::readFloatRegOperand(const StaticInst *si, int idx, int width)
-{
-    if (width == 32)
-        return (float)instSrc[idx].dbl;
-    else if (width == 64)
-        return instSrc[idx].dbl;
-    else {
-        panic("Unsupported Floating Point Width!");
-        return 0;
-    }
+InOrderDynInst::readFloatRegOperand(const StaticInst *si, int idx)
+{
+    return instSrc[idx].dbl;
 }
 
 
 /** Reads a FP register as a integer. */
 FloatRegBits
-InOrderDynInst::readFloatRegOperandBits(const StaticInst *si, int idx, int width)
+InOrderDynInst::readFloatRegOperandBits(const StaticInst *si, int idx)
 {
     return instSrc[idx].integer;
 }
@@ -507,31 +495,22 @@ InOrderDynInst::setIntRegOperand(const StaticInst *si, int idx, IntReg val)
 
 /** Sets a FP register. */
 void
-InOrderDynInst::setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, int width)
-{
-    if (width == 32) {
-        instResult[idx].val.dbl = (float)val;
-        instResult[idx].type = Float;
-    } else if (width == 64) {
-        instResult[idx].val.dbl = val;
-        instResult[idx].type = Double;
-    } else {
-        panic("Unsupported Floating Point Width!");
-    }
+InOrderDynInst::setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
+{
+    instResult[idx].val.dbl = val;
+    instResult[idx].type = Float;
 
     instResult[idx].tick = curTick;
-    instResult[idx].width = width;
 }
 
 /** Sets a FP register as a integer. */
 void
 InOrderDynInst::setFloatRegOperandBits(const StaticInst *si, int idx,
-                              FloatRegBits val, int width)
+                              FloatRegBits val)
 {
     instResult[idx].type = Integer;
     instResult[idx].val.integer = val;
     instResult[idx].tick = curTick;
-    instResult[idx].width = width;
 }
 
 /** Sets a misc. register. */
diff --git a/src/cpu/inorder/inorder_dyn_inst.hh b/src/cpu/inorder/inorder_dyn_inst.hh
index 031d882ee..e95a6d039 100644
--- a/src/cpu/inorder/inorder_dyn_inst.hh
+++ b/src/cpu/inorder/inorder_dyn_inst.hh
@@ -243,10 +243,9 @@ class InOrderDynInst : public FastAlloc, public RefCounted
         ResultType type;
         InstValue val;
         Tick tick;
-        int width;
 
         InstResult()
-            : type(None), tick(0), width(0)
+            : type(None), tick(0)
         {}
     };
 
@@ -817,7 +816,7 @@ class InOrderDynInst : public FastAlloc, public RefCounted
     /** Functions that sets an integer or floating point
      *  source register to a value. */
     void setIntSrc(int idx, uint64_t val);
-    void setFloatSrc(int idx, FloatReg val, int width = 32);
+    void setFloatSrc(int idx, FloatReg val);
     void setFloatRegBitsSrc(int idx, uint64_t val);
 
     uint64_t* getIntSrcPtr(int idx) { return &instSrc[idx].integer; }
@@ -830,10 +829,8 @@ class InOrderDynInst : public FastAlloc, public RefCounted
      *  the source reg. value is set using the setSrcReg() function.
      */
     IntReg readIntRegOperand(const StaticInst *si, int idx, ThreadID tid = 0);
-    FloatReg readFloatRegOperand(const StaticInst *si, int idx,
-                          int width = TheISA::SingleWidth);
-    TheISA::FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
-                                  int width = TheISA::SingleWidth);
+    FloatReg readFloatRegOperand(const StaticInst *si, int idx);
+    TheISA::FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx);
     MiscReg readMiscReg(int misc_reg);
     MiscReg readMiscRegNoEffect(int misc_reg);
     MiscReg readMiscRegOperand(const StaticInst *si, int idx);
@@ -853,15 +850,7 @@ class InOrderDynInst : public FastAlloc, public RefCounted
     /** Depending on type, return Float or Double */
     double readFloatResult(int idx)
     {
-        //Should this function have a parameter for what width of return?x
-       return (instResult[idx].type == Float) ?
-           (float) instResult[idx].val.dbl : instResult[idx].val.dbl;
-    }
-
-    double readDoubleResult(int idx)
-    {
-        assert(instResult[idx].type == Double);
-        return instResult[idx].val.dbl;
+       return instResult[idx].val.dbl;
     }
 
     Tick readResultTime(int idx) { return instResult[idx].tick; }
@@ -872,10 +861,9 @@ class InOrderDynInst : public FastAlloc, public RefCounted
      *  it's destination register.
      */
     void setIntRegOperand(const StaticInst *si, int idx, IntReg val);
-    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
-                     int width = TheISA::SingleWidth);
-    void setFloatRegOperandBits(const StaticInst *si, int idx, TheISA::FloatRegBits val,
-                         int width = TheISA::SingleWidth);
+    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val);
+    void setFloatRegOperandBits(const StaticInst *si, int idx,
+            TheISA::FloatRegBits val);
     void setMiscReg(int misc_reg, const MiscReg &val);
     void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
     void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val);
diff --git a/src/cpu/inorder/resources/execution_unit.cc b/src/cpu/inorder/resources/execution_unit.cc
index c9072b5d5..6c44e2456 100644
--- a/src/cpu/inorder/resources/execution_unit.cc
+++ b/src/cpu/inorder/resources/execution_unit.cc
@@ -179,8 +179,7 @@ ExecutionUnit::execute(int slot_num)
 
                     DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: The result of execution is 0x%x.\n",
                             inst->readTid(), seq_num, (inst->resultType(0) == InOrderDynInst::Float) ?
-                            inst->readFloatResult(0) : (inst->resultType(0) == InOrderDynInst::Double) ?
-                            inst->readDoubleResult(0) : inst->readIntResult(0));
+                            inst->readFloatResult(0) : inst->readIntResult(0));
 
                     exec_req->done();
                 } else {
diff --git a/src/cpu/inorder/resources/use_def.cc b/src/cpu/inorder/resources/use_def.cc
index b30a3a1bf..2f1652c08 100644
--- a/src/cpu/inorder/resources/use_def.cc
+++ b/src/cpu/inorder/resources/use_def.cc
@@ -53,8 +53,6 @@ UseDefUnit::UseDefUnit(string res_name, int res_id, int res_width,
         outWriteSeqNum[tid] = maxSeqNum;
 
         regDepMap[tid] = &cpu->archRegDepMap[tid];
-
-        floatRegSize[tid] = cpu->floatRegFile[tid].regWidth;
     }
 
 }
@@ -138,12 +136,11 @@ UseDefUnit::execute(int slot_idx)
                         DPRINTF(InOrderUseDef, "[tid:%i]: Reading Float Reg %i from Register File:%x (%08f).\n",
                                 tid,
                                 reg_idx,
-                                cpu->readFloatRegBits(reg_idx, inst->readTid(), floatRegSize[tid]),
-                                cpu->readFloatReg(reg_idx, inst->readTid(),floatRegSize[tid]));
+                                cpu->readFloatRegBits(reg_idx, inst->readTid()),
+                                cpu->readFloatReg(reg_idx, inst->readTid()));
 
                         inst->setFloatSrc(ud_idx,
-                                          cpu->readFloatReg(reg_idx, inst->readTid(), floatRegSize[tid]),
-                                          floatRegSize[tid]);
+                                          cpu->readFloatReg(reg_idx, inst->readTid()));
                     } else {
                         reg_idx -= Ctrl_Base_DepTag;
                         DPRINTF(InOrderUseDef, "[tid:%i]: Reading Misc Reg %i from Register File:%i.\n",
@@ -183,8 +180,7 @@ UseDefUnit::execute(int slot_idx)
                                     tid, forward_inst->readFloatResult(dest_reg_idx) ,
                                     forward_inst->seqNum, inst->seqNum, ud_idx);
                             inst->setFloatSrc(ud_idx,
-                                              forward_inst->readFloatResult(dest_reg_idx),
-                                              floatRegSize[tid]);
+                                              forward_inst->readFloatResult(dest_reg_idx));
                         } else {
                             DPRINTF(InOrderUseDef, "[tid:%i]: Forwarding dest. reg value 0x%x from "
                                     "[sn:%i] to [sn:%i] source #%i.\n",
@@ -244,24 +240,21 @@ UseDefUnit::execute(int slot_idx)
 
                             cpu->setFloatRegBits(reg_idx, // Check for FloatRegBits Here
                                              inst->readIntResult(ud_idx),
-                                             inst->readTid(),
-                                             floatRegSize[tid]);
+                                             inst->readTid());
                         } else if (inst->resultType(ud_idx) == InOrderDynInst::Float) {
                             DPRINTF(InOrderUseDef, "[tid:%i]: Writing Float Result 0x%x (bits:0x%x) to register idx %i.\n",
                                     tid, inst->readFloatResult(ud_idx), inst->readIntResult(ud_idx), reg_idx);
 
                             cpu->setFloatReg(reg_idx,
                                              inst->readFloatResult(ud_idx),
-                                             inst->readTid(),
-                                             floatRegSize[tid]);
+                                             inst->readTid());
                         } else if (inst->resultType(ud_idx) == InOrderDynInst::Double) {
                             DPRINTF(InOrderUseDef, "[tid:%i]: Writing Double Result 0x%x (bits:0x%x) to register idx %i.\n",
                                     tid, inst->readFloatResult(ud_idx), inst->readIntResult(ud_idx), reg_idx);
 
                             cpu->setFloatReg(reg_idx, // Check for FloatRegBits Here
-                                             inst->readDoubleResult(ud_idx),
-                                             inst->readTid(),
-                                             floatRegSize[tid]);
+                                             inst->readFloatResult(ud_idx),
+                                             inst->readTid());
                         } else {
                             panic("Result Type Not Set For [sn:%i] %s.\n", inst->seqNum, inst->instName());
                         }
diff --git a/src/cpu/inorder/thread_context.cc b/src/cpu/inorder/thread_context.cc
index a1e9b5948..fe1a0faa1 100644
--- a/src/cpu/inorder/thread_context.cc
+++ b/src/cpu/inorder/thread_context.cc
@@ -151,24 +151,12 @@ InOrderThreadContext::readIntReg(int reg_idx)
 }
 
 FloatReg
-InOrderThreadContext::readFloatReg(int reg_idx, int width)
-{
-    return cpu->readFloatReg(reg_idx, thread->readTid(), width);
-}
-
-FloatReg
 InOrderThreadContext::readFloatReg(int reg_idx)
 {
     return cpu->readFloatReg(reg_idx, thread->readTid());
 }
 
 FloatRegBits
-InOrderThreadContext::readFloatRegBits(int reg_idx, int width)
-{
-    return cpu->readFloatRegBits(reg_idx, thread->readTid(), width);
-}
-
-FloatRegBits
 InOrderThreadContext::readFloatRegBits(int reg_idx)
 {
     return cpu->readFloatRegBits(reg_idx, thread->readTid());
@@ -187,25 +175,12 @@ InOrderThreadContext::setIntReg(int reg_idx, uint64_t val)
 }
 
 void
-InOrderThreadContext::setFloatReg(int reg_idx, FloatReg val, int width)
-{
-    cpu->setFloatReg(reg_idx, val, thread->readTid(), width);
-}
-
-void
 InOrderThreadContext::setFloatReg(int reg_idx, FloatReg val)
 {
     cpu->setFloatReg(reg_idx, val, thread->readTid());
 }
 
 void
-InOrderThreadContext::setFloatRegBits(int reg_idx, FloatRegBits val,
-                                    int width)
-{
-    cpu->setFloatRegBits(reg_idx, val, thread->readTid(), width);
-}
-
-void
 InOrderThreadContext::setFloatRegBits(int reg_idx, FloatRegBits val)
 {
     cpu->setFloatRegBits(reg_idx, val, thread->readTid());
diff --git a/src/cpu/inorder/thread_context.hh b/src/cpu/inorder/thread_context.hh
index aac8901b3..327f8ac71 100644
--- a/src/cpu/inorder/thread_context.hh
+++ b/src/cpu/inorder/thread_context.hh
@@ -152,12 +152,8 @@ class InOrderThreadContext : public ThreadContext
     /** Reads an integer register. */
     virtual uint64_t readIntReg(int reg_idx);
 
-    virtual FloatReg readFloatReg(int reg_idx, int width);
-
     virtual FloatReg readFloatReg(int reg_idx);
 
-    virtual FloatRegBits readFloatRegBits(int reg_idx, int width);
-
     virtual FloatRegBits readFloatRegBits(int reg_idx);
 
     virtual uint64_t readRegOtherThread(int misc_reg, ThreadID tid);
@@ -165,12 +161,8 @@ class InOrderThreadContext : public ThreadContext
     /** Sets an integer register to a value. */
     virtual void setIntReg(int reg_idx, uint64_t val);
 
-    virtual void setFloatReg(int reg_idx, FloatReg val, int width);
-
     virtual void setFloatReg(int reg_idx, FloatReg val);
 
-    virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width);
-
     virtual void setFloatRegBits(int reg_idx, FloatRegBits val);
 
     virtual void setRegOtherThread(int misc_reg, const MiscReg &val,
diff --git a/src/cpu/legiontrace.cc b/src/cpu/legiontrace.cc
index 0ca02eeec..f40e776d2 100644
--- a/src/cpu/legiontrace.cc
+++ b/src/cpu/legiontrace.cc
@@ -232,8 +232,7 @@ Trace::LegionTraceRecord::dump()
                     }
                 }
                 for (int i = 0; i < TheISA::NumFloatRegs/2; i++) {
-                    if (thread->readFloatRegBits(i*2,
-                                FloatRegFile::DoubleWidth) !=
+                    if (thread->readFloatRegBits(i*2) !=
                             shared_data->fpregs[i]) {
                         diffFpRegs = true;
                     }
@@ -539,8 +538,7 @@ Trace::LegionTraceRecord::dump()
                             char label[8];
                             sprintf(label, "%%f%d", x);
                             printRegPair(outs, label,
-                                thread->readFloatRegBits(x*2,
-                                    FloatRegFile::DoubleWidth),
+                                thread->readFloatRegBits(x*2),
                                 shared_data->fpregs[x]);
                         }
                     }
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 2f8869b6f..394efe16a 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1215,13 +1215,6 @@ FullO3CPU<Impl>::readIntReg(int reg_idx)
 
 template <class Impl>
 FloatReg
-FullO3CPU<Impl>::readFloatReg(int reg_idx, int width)
-{
-    return regFile.readFloatReg(reg_idx, width);
-}
-
-template <class Impl>
-FloatReg
 FullO3CPU<Impl>::readFloatReg(int reg_idx)
 {
     return regFile.readFloatReg(reg_idx);
@@ -1229,13 +1222,6 @@ FullO3CPU<Impl>::readFloatReg(int reg_idx)
 
 template <class Impl>
 FloatRegBits
-FullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width)
-{
-    return regFile.readFloatRegBits(reg_idx, width);
-}
-
-template <class Impl>
-FloatRegBits
 FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
 {
     return regFile.readFloatRegBits(reg_idx);
@@ -1250,13 +1236,6 @@ FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
 
 template <class Impl>
 void
-FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width)
-{
-    regFile.setFloatReg(reg_idx, val, width);
-}
-
-template <class Impl>
-void
 FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
 {
     regFile.setFloatReg(reg_idx, val);
@@ -1264,13 +1243,6 @@ FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
 
 template <class Impl>
 void
-FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width)
-{
-    regFile.setFloatRegBits(reg_idx, val, width);
-}
-
-template <class Impl>
-void
 FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
 {
     regFile.setFloatRegBits(reg_idx, val);
@@ -1287,7 +1259,7 @@ FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
 
 template <class Impl>
 float
-FullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, ThreadID tid)
+FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
 {
     int idx = reg_idx + TheISA::NumIntRegs;
     PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
@@ -1296,16 +1268,6 @@ FullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, ThreadID tid)
 }
 
 template <class Impl>
-double
-FullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, ThreadID tid)
-{
-    int idx = reg_idx + TheISA::NumIntRegs;
-    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
-
-    return regFile.readFloatReg(phys_reg, 64);
-}
-
-template <class Impl>
 uint64_t
 FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
 {
@@ -1326,7 +1288,7 @@ FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
 
 template <class Impl>
 void
-FullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, ThreadID tid)
+FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
 {
     int idx = reg_idx + TheISA::NumIntRegs;
     PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
@@ -1336,16 +1298,6 @@ FullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, ThreadID tid)
 
 template <class Impl>
 void
-FullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, ThreadID tid)
-{
-    int idx = reg_idx + TheISA::NumIntRegs;
-    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
-
-    regFile.setFloatReg(phys_reg, val, 64);
-}
-
-template <class Impl>
-void
 FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
 {
     int idx = reg_idx + TheISA::NumIntRegs;
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 1289785dc..c077b2493 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -435,27 +435,17 @@ class FullO3CPU : public BaseO3CPU
 
     TheISA::FloatReg readFloatReg(int reg_idx);
 
-    TheISA::FloatReg readFloatReg(int reg_idx, int width);
-
     TheISA::FloatRegBits readFloatRegBits(int reg_idx);
 
-    TheISA::FloatRegBits readFloatRegBits(int reg_idx, int width);
-
     void setIntReg(int reg_idx, uint64_t val);
 
     void setFloatReg(int reg_idx, TheISA::FloatReg val);
 
-    void setFloatReg(int reg_idx, TheISA::FloatReg val, int width);
-
     void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
 
-    void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val, int width);
-
     uint64_t readArchIntReg(int reg_idx, ThreadID tid);
 
-    float readArchFloatRegSingle(int reg_idx, ThreadID tid);
-
-    double readArchFloatRegDouble(int reg_idx, ThreadID tid);
+    float readArchFloatReg(int reg_idx, ThreadID tid);
 
     uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid);
 
@@ -466,9 +456,7 @@ class FullO3CPU : public BaseO3CPU
      */
     void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid);
 
-    void setArchFloatRegSingle(int reg_idx, float val, ThreadID tid);
-
-    void setArchFloatRegDouble(int reg_idx, double val, ThreadID tid);
+    void setArchFloatReg(int reg_idx, float val, ThreadID tid);
 
     void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);
 
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 292547b6b..3ef42e91f 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -196,22 +196,11 @@ class BaseO3DynInst : public BaseDynInst<Impl>
         return this->cpu->readIntReg(this->_srcRegIdx[idx]);
     }
 
-    FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
-    {
-        return this->cpu->readFloatReg(this->_srcRegIdx[idx], width);
-    }
-
     FloatReg readFloatRegOperand(const StaticInst *si, int idx)
     {
         return this->cpu->readFloatReg(this->_srcRegIdx[idx]);
     }
 
-    FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
-                                         int width)
-    {
-        return this->cpu->readFloatRegBits(this->_srcRegIdx[idx], width);
-    }
-
     FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
     {
         return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]);
@@ -226,13 +215,6 @@ class BaseO3DynInst : public BaseDynInst<Impl>
         BaseDynInst<Impl>::setIntRegOperand(si, idx, val);
     }
 
-    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
-                            int width)
-    {
-        this->cpu->setFloatReg(this->_destRegIdx[idx], val, width);
-        BaseDynInst<Impl>::setFloatRegOperand(si, idx, val, width);
-    }
-
     void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
     {
         this->cpu->setFloatReg(this->_destRegIdx[idx], val);
@@ -240,13 +222,6 @@ class BaseO3DynInst : public BaseDynInst<Impl>
     }
 
     void setFloatRegOperandBits(const StaticInst *si, int idx,
-                                FloatRegBits val, int width)
-    {
-        this->cpu->setFloatRegBits(this->_destRegIdx[idx], val, width);
-        BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
-    }
-
-    void setFloatRegOperandBits(const StaticInst *si, int idx,
                                 FloatRegBits val)
     {
         this->cpu->setFloatRegBits(this->_destRegIdx[idx], val);
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index e7b20e4a9..44c349ef4 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -93,21 +93,6 @@ class PhysRegFile
         return intRegFile[reg_idx];
     }
 
-    FloatReg readFloatReg(PhysRegIndex reg_idx, int width)
-    {
-        // Remove the base Float reg dependency.
-        reg_idx = reg_idx - numPhysicalIntRegs;
-
-        assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
-
-        FloatReg floatReg = floatRegFile[reg_idx].d;
-
-        DPRINTF(IEW, "RegFile: Access to %d byte float register %i, has "
-                "data %#x\n", int(reg_idx), floatRegFile[reg_idx].q);
-
-        return floatReg;
-    }
-
     /** Reads a floating point register (double precision). */
     FloatReg readFloatReg(PhysRegIndex reg_idx)
     {
@@ -124,22 +109,6 @@ class PhysRegFile
         return floatReg;
     }
 
-    /** Reads a floating point register as an integer. */
-    FloatRegBits readFloatRegBits(PhysRegIndex reg_idx, int width)
-    {
-        // Remove the base Float reg dependency.
-        reg_idx = reg_idx - numPhysicalIntRegs;
-
-        assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
-
-        FloatRegBits floatRegBits = floatRegFile[reg_idx].q;
-
-        DPRINTF(IEW, "RegFile: Access to float register %i as int, "
-                "has data %#x\n", int(reg_idx), (uint64_t)floatRegBits);
-
-        return floatRegBits;
-    }
-
     FloatRegBits readFloatRegBits(PhysRegIndex reg_idx)
     {
         // Remove the base Float reg dependency.
@@ -167,23 +136,6 @@ class PhysRegFile
             intRegFile[reg_idx] = val;
     }
 
-    /** Sets a single precision floating point register to the given value. */
-    void setFloatReg(PhysRegIndex reg_idx, FloatReg val, int width)
-    {
-        // Remove the base Float reg dependency.
-        reg_idx = reg_idx - numPhysicalIntRegs;
-
-        assert(reg_idx < numPhysicalFloatRegs);
-
-        DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
-                int(reg_idx), (uint64_t)val);
-
-#if THE_ISA == ALPHA_ISA
-        if (reg_idx != TheISA::ZeroReg)
-#endif
-            floatRegFile[reg_idx].d = val;
-    }
-
     /** Sets a double precision floating point register to the given value. */
     void setFloatReg(PhysRegIndex reg_idx, FloatReg val)
     {
@@ -201,20 +153,6 @@ class PhysRegFile
             floatRegFile[reg_idx].d = val;
     }
 
-    /** Sets a floating point register to the given integer value. */
-    void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val, int width)
-    {
-        // Remove the base Float reg dependency.
-        reg_idx = reg_idx - numPhysicalIntRegs;
-
-        assert(reg_idx < numPhysicalFloatRegs);
-
-        DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
-                int(reg_idx), (uint64_t)val);
-
-        floatRegFile[reg_idx].q = val;
-    }
-
     void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val)
     {
         // Remove the base Float reg dependency.
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index a3f1ce58f..ed5c6ac20 100755
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -167,23 +167,15 @@ class O3ThreadContext : public ThreadContext
     /** Reads an integer register. */
     virtual uint64_t readIntReg(int reg_idx);
 
-    virtual FloatReg readFloatReg(int reg_idx, int width);
-
     virtual FloatReg readFloatReg(int reg_idx);
 
-    virtual FloatRegBits readFloatRegBits(int reg_idx, int width);
-
     virtual FloatRegBits readFloatRegBits(int reg_idx);
 
     /** Sets an integer register to a value. */
     virtual void setIntReg(int reg_idx, uint64_t val);
 
-    virtual void setFloatReg(int reg_idx, FloatReg val, int width);
-
     virtual void setFloatReg(int reg_idx, FloatReg val);
 
-    virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width);
-
     virtual void setFloatRegBits(int reg_idx, FloatRegBits val);
 
     /** Reads this thread's PC. */
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index 6527f5d06..0b5eddc73 100755
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -278,35 +278,10 @@ O3ThreadContext<Impl>::readIntReg(int reg_idx)
 
 template <class Impl>
 TheISA::FloatReg
-O3ThreadContext<Impl>::readFloatReg(int reg_idx, int width)
-{
-    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
-    switch(width) {
-      case 32:
-        return cpu->readArchFloatRegSingle(reg_idx, thread->threadId());
-      case 64:
-        return cpu->readArchFloatRegDouble(reg_idx, thread->threadId());
-      default:
-        panic("Unsupported width!");
-        return 0;
-    }
-}
-
-template <class Impl>
-TheISA::FloatReg
 O3ThreadContext<Impl>::readFloatReg(int reg_idx)
 {
     reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
-    return cpu->readArchFloatRegSingle(reg_idx, thread->threadId());
-}
-
-template <class Impl>
-TheISA::FloatRegBits
-O3ThreadContext<Impl>::readFloatRegBits(int reg_idx, int width)
-{
-    DPRINTF(Fault, "Reading floatint register through the TC!\n");
-    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
-    return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
+    return cpu->readArchFloatReg(reg_idx, thread->threadId());
 }
 
 template <class Impl>
@@ -332,30 +307,10 @@ O3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val)
 
 template <class Impl>
 void
-O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val, int width)
-{
-    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
-    switch(width) {
-      case 32:
-        cpu->setArchFloatRegSingle(reg_idx, val, thread->threadId());
-        break;
-      case 64:
-        cpu->setArchFloatRegDouble(reg_idx, val, thread->threadId());
-        break;
-    }
-
-    // Squash if we're not already in a state update mode.
-    if (!thread->trapPending && !thread->inSyscall) {
-        cpu->squashFromTC(thread->threadId());
-    }
-}
-
-template <class Impl>
-void
 O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val)
 {
     reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
-    cpu->setArchFloatRegSingle(reg_idx, val, thread->threadId());
+    cpu->setArchFloatReg(reg_idx, val, thread->threadId());
 
     if (!thread->trapPending && !thread->inSyscall) {
         cpu->squashFromTC(thread->threadId());
@@ -364,21 +319,6 @@ O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val)
 
 template <class Impl>
 void
-O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val,
-                                             int width)
-{
-    DPRINTF(Fault, "Setting floatint register through the TC!\n");
-    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
-    cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
-
-    // Squash if we're not already in a state update mode.
-    if (!thread->trapPending && !thread->inSyscall) {
-        cpu->squashFromTC(thread->threadId());
-    }
-}
-
-template <class Impl>
-void
 O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
 {
     reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index 2e21411ae..62e6f6e5a 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -183,22 +183,14 @@ class OzoneCPU : public BaseCPU
 
         uint64_t readIntReg(int reg_idx);
 
-        FloatReg readFloatReg(int reg_idx, int width);
-
         FloatReg readFloatReg(int reg_idx);
 
-        FloatRegBits readFloatRegBits(int reg_idx, int width);
-
         FloatRegBits readFloatRegBits(int reg_idx);
 
         void setIntReg(int reg_idx, uint64_t val);
 
-        void setFloatReg(int reg_idx, FloatReg val, int width);
-
         void setFloatReg(int reg_idx, FloatReg val);
 
-        void setFloatRegBits(int reg_idx, FloatRegBits val, int width);
-
         void setFloatRegBits(int reg_idx, FloatRegBits val);
 
         uint64_t readPC() { return thread->PC; }
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index 25fa64071..f86b882d1 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -918,22 +918,6 @@ OzoneCPU<Impl>::OzoneTC::readIntReg(int reg_idx)
 }
 
 template <class Impl>
-TheISA::FloatReg
-OzoneCPU<Impl>::OzoneTC::readFloatReg(int reg_idx, int width)
-{
-    int idx = reg_idx + TheISA::FP_Base_DepTag;
-    switch(width) {
-      case 32:
-        return thread->renameTable[idx]->readFloatResult();
-      case 64:
-        return thread->renameTable[idx]->readDoubleResult();
-      default:
-        panic("Unsupported width!");
-        return 0;
-    }
-}
-
-template <class Impl>
 double
 OzoneCPU<Impl>::OzoneTC::readFloatReg(int reg_idx)
 {
@@ -943,14 +927,6 @@ OzoneCPU<Impl>::OzoneTC::readFloatReg(int reg_idx)
 
 template <class Impl>
 uint64_t
-OzoneCPU<Impl>::OzoneTC::readFloatRegBits(int reg_idx, int width)
-{
-    int idx = reg_idx + TheISA::FP_Base_DepTag;
-    return thread->renameTable[idx]->readIntResult();
-}
-
-template <class Impl>
-uint64_t
 OzoneCPU<Impl>::OzoneTC::readFloatRegBits(int reg_idx)
 {
     int idx = reg_idx + TheISA::FP_Base_DepTag;
@@ -970,27 +946,6 @@ OzoneCPU<Impl>::OzoneTC::setIntReg(int reg_idx, uint64_t val)
 
 template <class Impl>
 void
-OzoneCPU<Impl>::OzoneTC::setFloatReg(int reg_idx, FloatReg val, int width)
-{
-    int idx = reg_idx + TheISA::FP_Base_DepTag;
-    switch(width) {
-      case 32:
-        panic("Unimplemented!");
-        break;
-      case 64:
-        thread->renameTable[idx]->setDoubleResult(val);
-        break;
-      default:
-        panic("Unsupported width!");
-    }
-
-    if (!thread->inSyscall) {
-        cpu->squashFromTC();
-    }
-}
-
-template <class Impl>
-void
 OzoneCPU<Impl>::OzoneTC::setFloatReg(int reg_idx, FloatReg val)
 {
     int idx = reg_idx + TheISA::FP_Base_DepTag;
@@ -1004,14 +959,6 @@ OzoneCPU<Impl>::OzoneTC::setFloatReg(int reg_idx, FloatReg val)
 
 template <class Impl>
 void
-OzoneCPU<Impl>::OzoneTC::setFloatRegBits(int reg_idx, FloatRegBits val,
-                                         int width)
-{
-    panic("Unimplemented!");
-}
-
-template <class Impl>
-void
 OzoneCPU<Impl>::OzoneTC::setFloatRegBits(int reg_idx, FloatRegBits val)
 {
     panic("Unimplemented!");
diff --git a/src/cpu/ozone/dyn_inst.hh b/src/cpu/ozone/dyn_inst.hh
index e138cbe13..a39f383ba 100644
--- a/src/cpu/ozone/dyn_inst.hh
+++ b/src/cpu/ozone/dyn_inst.hh
@@ -151,28 +151,14 @@ class OzoneDynInst : public BaseDynInst<Impl>
         return srcInsts[idx]->readIntResult();
     }
 
-    FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
-    {
-        switch(width) {
-          case 32:
-            return srcInsts[idx]->readFloatResult();
-          case 64:
-            return srcInsts[idx]->readDoubleResult();
-          default:
-            panic("Width not supported");
-            return 0;
-        }
-    }
-
     FloatReg readFloatRegOperand(const StaticInst *si, int idx)
     {
         return srcInsts[idx]->readFloatResult();
     }
 
-    FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
-                                         int width)
+    FloatReg readFloatRegOperand(const StaticInst *si, int idx)
     {
-        return srcInsts[idx]->readIntResult();
+        return srcInsts[idx]->readFloatResult();
     }
 
     FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
@@ -188,24 +174,12 @@ class OzoneDynInst : public BaseDynInst<Impl>
         BaseDynInst<Impl>::setIntReg(si, idx, val);
     }
 
-    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
-                            int width)
-    {
-        BaseDynInst<Impl>::setFloatReg(si, idx, val, width);
-    }
-
     void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
     {
         BaseDynInst<Impl>::setFloatReg(si, idx, val);
     }
 
     void setFloatRegOperandBits(const StaticInst *si, int idx,
-                                FloatRegBits val, int width)
-    {
-        BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
-    }
-
-    void setFloatRegOperandBits(const StaticInst *si, int idx,
                                 FloatRegBits val)
     {
         BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 4e71d677e..466d0d1c9 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -262,25 +262,12 @@ class BaseSimpleCPU : public BaseCPU
         return thread->readIntReg(si->srcRegIdx(idx));
     }
 
-    FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
-    {
-        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
-        return thread->readFloatReg(reg_idx, width);
-    }
-
     FloatReg readFloatRegOperand(const StaticInst *si, int idx)
     {
         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
         return thread->readFloatReg(reg_idx);
     }
 
-    FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
-                                         int width)
-    {
-        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
-        return thread->readFloatRegBits(reg_idx, width);
-    }
-
     FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
     {
         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
@@ -292,13 +279,6 @@ class BaseSimpleCPU : public BaseCPU
         thread->setIntReg(si->destRegIdx(idx), val);
     }
 
-    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
-                            int width)
-    {
-        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
-        thread->setFloatReg(reg_idx, val, width);
-    }
-
     void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
     {
         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
@@ -306,13 +286,6 @@ class BaseSimpleCPU : public BaseCPU
     }
 
     void setFloatRegOperandBits(const StaticInst *si, int idx,
-                                FloatRegBits val, int width)
-    {
-        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
-        thread->setFloatRegBits(reg_idx, val, width);
-    }
-
-    void setFloatRegOperandBits(const StaticInst *si, int idx,
                                 FloatRegBits val)
     {
         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 3199263be..06cfd3fbb 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -234,24 +234,12 @@ class SimpleThread : public ThreadState
         return regs.readIntReg(flatIndex);
     }
 
-    FloatReg readFloatReg(int reg_idx, int width)
-    {
-        int flatIndex = isa.flattenFloatIndex(reg_idx);
-        return regs.readFloatReg(flatIndex, width);
-    }
-
     FloatReg readFloatReg(int reg_idx)
     {
         int flatIndex = isa.flattenFloatIndex(reg_idx);
         return regs.readFloatReg(flatIndex);
     }
 
-    FloatRegBits readFloatRegBits(int reg_idx, int width)
-    {
-        int flatIndex = isa.flattenFloatIndex(reg_idx);
-        return regs.readFloatRegBits(flatIndex, width);
-    }
-
     FloatRegBits readFloatRegBits(int reg_idx)
     {
         int flatIndex = isa.flattenFloatIndex(reg_idx);
@@ -264,24 +252,12 @@ class SimpleThread : public ThreadState
         regs.setIntReg(flatIndex, val);
     }
 
-    void setFloatReg(int reg_idx, FloatReg val, int width)
-    {
-        int flatIndex = isa.flattenFloatIndex(reg_idx);
-        regs.setFloatReg(flatIndex, val, width);
-    }
-
     void setFloatReg(int reg_idx, FloatReg val)
     {
         int flatIndex = isa.flattenFloatIndex(reg_idx);
         regs.setFloatReg(flatIndex, val);
     }
 
-    void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
-    {
-        int flatIndex = isa.flattenFloatIndex(reg_idx);
-        regs.setFloatRegBits(flatIndex, val, width);
-    }
-
     void setFloatRegBits(int reg_idx, FloatRegBits val)
     {
         int flatIndex = isa.flattenFloatIndex(reg_idx);
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 8963553d5..49776858d 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -187,24 +187,16 @@ class ThreadContext
     //
     virtual uint64_t readIntReg(int reg_idx) = 0;
 
-    virtual FloatReg readFloatReg(int reg_idx, int width) = 0;
-
     virtual FloatReg readFloatReg(int reg_idx) = 0;
 
-    virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0;
-
     virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
 
     virtual void setIntReg(int reg_idx, uint64_t val) = 0;
 
-    virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0;
-
     virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
 
     virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
 
-    virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0;
-
     virtual uint64_t readPC() = 0;
 
     virtual void setPC(uint64_t val) = 0;
@@ -377,30 +369,18 @@ class ProxyThreadContext : public ThreadContext
     uint64_t readIntReg(int reg_idx)
     { return actualTC->readIntReg(reg_idx); }
 
-    FloatReg readFloatReg(int reg_idx, int width)
-    { return actualTC->readFloatReg(reg_idx, width); }
-
     FloatReg readFloatReg(int reg_idx)
     { return actualTC->readFloatReg(reg_idx); }
 
-    FloatRegBits readFloatRegBits(int reg_idx, int width)
-    { return actualTC->readFloatRegBits(reg_idx, width); }
-
     FloatRegBits readFloatRegBits(int reg_idx)
     { return actualTC->readFloatRegBits(reg_idx); }
 
     void setIntReg(int reg_idx, uint64_t val)
     { actualTC->setIntReg(reg_idx, val); }
 
-    void setFloatReg(int reg_idx, FloatReg val, int width)
-    { actualTC->setFloatReg(reg_idx, val, width); }
-
     void setFloatReg(int reg_idx, FloatReg val)
     { actualTC->setFloatReg(reg_idx, val); }
 
-    void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
-    { actualTC->setFloatRegBits(reg_idx, val, width); }
-
     void setFloatRegBits(int reg_idx, FloatRegBits val)
     { actualTC->setFloatRegBits(reg_idx, val); }