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| author | Ron Dreslinski <rdreslin@umich.edu> | 2006-07-06 15:15:37 -0400 |
|---|---|---|
| committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-07-06 15:15:37 -0400 |
| commit | 329e32f8c63a5982b29c2d620e7d08708ec62fbd (patch) | |
| tree | 9f77df5b3d07dfdcb309b98984c0c4dc3b4300df /src/cpu | |
| parent | 4201ec84b2dd7d96148bf661124dd7b5d0e7204b (diff) | |
| download | gem5-329e32f8c63a5982b29c2d620e7d08708ec62fbd.tar.xz | |
Now timing reads work in single level of cache with simple cpu
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.hh:
Changes to handle timing reads in Simple CPU (blocking buffers)
--HG--
extra : convert_revision : a2e7d4287d7cdfd1bbf9c929ecbeafde499a5b9f
Diffstat (limited to 'src/cpu')
0 files changed, 0 insertions, 0 deletions