Implement Niagara I/O interface and rework interrupts

configs/common/FSConfig.py:
    Use binaries we've compiled instead of the ones that come with Legion
src/arch/alpha/interrupts.hh:
    get rid of post(int int_type) and add a get_vec function that gets the interrupt vector for an interrupt number
src/arch/sparc/asi.cc:
    Add AsiIsInterrupt() to AsiIsMmu()
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
    Add InterruptVector type
src/arch/sparc/interrupts.hh:
    rework interrupts. They are no longer cleared when created... A I/O or ASI read/write needs to happen before they are cleared
src/arch/sparc/isa_traits.hh:
    Add the "interrupt" trap types to isa traits
src/arch/sparc/miscregfile.cc:
    add names for all the misc registers and possible post an interrupt when TL is changed.
src/arch/sparc/miscregfile.hh:
    Add a helper function to post an interrupt when pil < some set softint
src/arch/sparc/regfile.cc:
src/arch/sparc/regfile.hh:
    InterruptLevel shouldn't really live here, moved to interrupt.hh
src/arch/sparc/tlb.cc:
    Add interrupt ASIs to TLB
src/arch/sparc/ua2005.cc:
    Add checkSoftInt to check if a softint needs to be posted
    Check that a tickCompare isn't scheduled before scheduling one
    Post and clear interrupts on queue writes and what not
src/base/bitfield.hh:
    Add an helper function to return the msb that is set
src/cpu/base.cc:
src/cpu/base.hh:
    get rid of post_interrupt(type) since it's no longer needed.. Add a way to see what interrupts are pending
src/cpu/intr_control.cc:
src/cpu/intr_control.hh:
src/dev/alpha/tsunami_cchip.cc:
src/python/m5/objects/IntrControl.py:
    Make IntrControl have a system pointer rather than using a cpu pointer to get one
src/dev/sparc/SConscript:
    add iob to SConsscrip
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out:
    update config.ini/out for intrcntrl not having a cpu pointer anymore

--HG--
extra : convert_revision : 38614f6b9ffc8f3c93949a94ff04b7d2987168dd

4 files changed, 17 insertions, 22 deletions

diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index d5a023c59..104b3b6bb 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -372,12 +372,6 @@ BaseCPU::ProfileEvent::process()
 }
 
 void
-BaseCPU::post_interrupt(int int_type)
-{
-    interrupts.post(int_type);
-}
-
-void
 BaseCPU::post_interrupt(int int_num, int index)
 {
     interrupts.post(int_num, index);
@@ -395,6 +389,11 @@ BaseCPU::clear_interrupts()
     interrupts.clear_all();
 }
 
+uint64_t
+BaseCPU::get_interrupts(int int_num)
+{
+    return interrupts.get_vec(int_num);
+}
 
 void
 BaseCPU::serialize(std::ostream &os)
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index a1265b748..d4213887d 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -102,10 +102,10 @@ class BaseCPU : public MemObject
     TheISA::Interrupts interrupts;
 
   public:
-    virtual void post_interrupt(int int_type);
     virtual void post_interrupt(int int_num, int index);
     virtual void clear_interrupt(int int_num, int index);
     virtual void clear_interrupts();
+    virtual uint64_t get_interrupts(int int_num);
 
     bool check_interrupts(ThreadContext * tc) const
     { return interrupts.check_interrupts(tc); }
diff --git a/src/cpu/intr_control.cc b/src/cpu/intr_control.cc
index 4cbc86891..be0f6599b 100644
--- a/src/cpu/intr_control.cc
+++ b/src/cpu/intr_control.cc
@@ -40,18 +40,14 @@
 
 using namespace std;
 
-IntrControl::IntrControl(const string &name, BaseCPU *c)
-    : SimObject(name), cpu(c)
+IntrControl::IntrControl(const string &name, System *s)
+    : SimObject(name), sys(s)
 {}
 
-/* @todo
- *Fix the cpu sim object parameter to be a system pointer
- *instead, to avoid some extra dereferencing
- */
 void
 IntrControl::post(int int_num, int index)
 {
-    std::vector<ThreadContext *> &tcvec = cpu->system->threadContexts;
+    std::vector<ThreadContext *> &tcvec = sys->threadContexts;
     BaseCPU *temp = tcvec[0]->getCpuPtr();
     temp->post_interrupt(int_num, index);
 }
@@ -59,7 +55,7 @@ IntrControl::post(int int_num, int index)
 void
 IntrControl::post(int cpu_id, int int_num, int index)
 {
-    std::vector<ThreadContext *> &tcvec = cpu->system->threadContexts;
+    std::vector<ThreadContext *> &tcvec = sys->threadContexts;
     BaseCPU *temp = tcvec[cpu_id]->getCpuPtr();
     temp->post_interrupt(int_num, index);
 }
@@ -67,7 +63,7 @@ IntrControl::post(int cpu_id, int int_num, int index)
 void
 IntrControl::clear(int int_num, int index)
 {
-    std::vector<ThreadContext *> &tcvec = cpu->system->threadContexts;
+    std::vector<ThreadContext *> &tcvec = sys->threadContexts;
     BaseCPU *temp = tcvec[0]->getCpuPtr();
     temp->clear_interrupt(int_num, index);
 }
@@ -75,26 +71,26 @@ IntrControl::clear(int int_num, int index)
 void
 IntrControl::clear(int cpu_id, int int_num, int index)
 {
-    std::vector<ThreadContext *> &tcvec = cpu->system->threadContexts;
+    std::vector<ThreadContext *> &tcvec = sys->threadContexts;
     BaseCPU *temp = tcvec[cpu_id]->getCpuPtr();
     temp->clear_interrupt(int_num, index);
 }
 
 BEGIN_DECLARE_SIM_OBJECT_PARAMS(IntrControl)
 
-    SimObjectParam<BaseCPU *> cpu;
+    SimObjectParam<System *> sys;
 
 END_DECLARE_SIM_OBJECT_PARAMS(IntrControl)
 
 BEGIN_INIT_SIM_OBJECT_PARAMS(IntrControl)
 
-    INIT_PARAM(cpu, "the cpu")
+    INIT_PARAM(sys, "the system we are part of")
 
 END_INIT_SIM_OBJECT_PARAMS(IntrControl)
 
 CREATE_SIM_OBJECT(IntrControl)
 {
-    return new IntrControl(getInstanceName(), cpu);
+    return new IntrControl(getInstanceName(), sys);
 }
 
 REGISTER_SIM_OBJECT("IntrControl", IntrControl)
diff --git a/src/cpu/intr_control.hh b/src/cpu/intr_control.hh
index 2e3f9e038..c6f75abf0 100644
--- a/src/cpu/intr_control.hh
+++ b/src/cpu/intr_control.hh
@@ -42,8 +42,8 @@
 class IntrControl : public SimObject
 {
   public:
-    BaseCPU *cpu;
-    IntrControl(const std::string &name, BaseCPU *c);
+    System *sys;
+    IntrControl(const std::string &name, System *s);
 
     void clear(int int_num, int index = 0);
     void post(int int_num, int index = 0);