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| author | Xiaoyu Ma <xiaoyuma@google.com> | 2017-11-30 07:48:52 -0800 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2018-01-12 00:57:56 +0000 |
| commit | 5320a97ced43d4452014ff54c0ba45246db90a00 (patch) | |
| tree | 8048a3c9f79b83deb64b7c5454bd560b2b115208 /src/cpu | |
| parent | cc51037e8074949bc9e7638babfb597490d007ec (diff) | |
| download | gem5-5320a97ced43d4452014ff54c0ba45246db90a00.tar.xz | |
sim: Allow passing a user-defined L2XBar to addTwoLevelCacheHierarchy().
Before this CL, the addTwoLevelCacheHierarchy() function uses the
default L2XBar class as the interconnect between CPU L1 caches and
L2. This CL allows passing a user-defined bus to overwrite the
default L2XBar by adding an optional argument to the function.
Change-Id: I917657272fd4924ee0bed882a226851afba26847
Reviewed-on: https://gem5-review.googlesource.com/7364
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/BaseCPU.py | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index c100f0ed5..3e82daf29 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -299,9 +299,10 @@ class BaseCPU(MemObject): self._cached_ports += ["checker.itb.walker.port", \ "checker.dtb.walker.port"] - def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): + def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc=None, dwc=None, + xbar=None): self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) - self.toL2Bus = L2XBar() + self.toL2Bus = xbar if xbar else L2XBar() self.connectCachedPorts(self.toL2Bus) self.l2cache = l2c self.toL2Bus.master = self.l2cache.cpu_side |