Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.

--HG--
extra : convert_revision : a04a30df0b6246e877a1cea35420dbac94b506b1

26 files changed, 82 insertions, 123 deletions

diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 7a51650e6..9b2b99c58 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -37,12 +37,14 @@ import sys
 
 default_tracer = ExeTracer()
 
-if build_env['FULL_SYSTEM']:
-    if build_env['TARGET_ISA'] == 'alpha':
-        from AlphaTLB import AlphaDTB, AlphaITB
-
-    if build_env['TARGET_ISA'] == 'sparc':
-        from SparcTLB import SparcDTB, SparcITB
+if build_env['TARGET_ISA'] == 'alpha':
+    from AlphaTLB import AlphaDTB, AlphaITB
+elif build_env['TARGET_ISA'] == 'sparc':
+    from SparcTLB import SparcDTB, SparcITB
+elif build_env['TARGET_ISA'] == 'x86':
+    from X86TLB import X86DTB, X86ITB
+elif build_env['TARGET_ISA'] == 'mips':
+    from MipsTLB import MipsDTB, MipsITB
 
 class BaseCPU(SimObject):
     type = 'BaseCPU'
@@ -57,19 +59,26 @@ class BaseCPU(SimObject):
             "enable checkpoint pseudo instructions")
         do_statistics_insts = Param.Bool(True,
             "enable statistics pseudo instructions")
-
-        if build_env['TARGET_ISA'] == 'sparc':
-            dtb = Param.SparcDTB(SparcDTB(), "Data TLB")
-            itb = Param.SparcITB(SparcITB(), "Instruction TLB")
-        elif build_env['TARGET_ISA'] == 'alpha':
-            dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB")
-            itb = Param.AlphaITB(AlphaITB(), "Instruction TLB")
-        else:
-            print "Unknown architecture, can't pick TLBs"
-            sys.exit(1)
     else:
         workload = VectorParam.Process("processes to run")
 
+    if build_env['TARGET_ISA'] == 'sparc':
+        dtb = Param.SparcDTB(SparcDTB(), "Data TLB")
+        itb = Param.SparcITB(SparcITB(), "Instruction TLB")
+    elif build_env['TARGET_ISA'] == 'alpha':
+        dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB")
+        itb = Param.AlphaITB(AlphaITB(), "Instruction TLB")
+    elif build_env['TARGET_ISA'] == 'x86':
+        dtb = Param.X86DTB(X86DTB(), "Data TLB")
+        itb = Param.X86ITB(X86ITB(), "Instruction TLB")
+    elif build_env['TARGET_ISA'] == 'mips':
+        dtb = Param.MipsDTB(MipsDTB(), "Data TLB")
+        itb = Param.MipsITB(MipsITB(), "Instruction TLB")
+    else:
+        print "Don't know what TLB to use for ISA %s" % \
+            build_env['TARGET_ISA']
+        sys.exit(1)
+
     max_insts_all_threads = Param.Counter(0,
         "terminate when all threads have reached this inst count")
     max_insts_any_thread = Param.Counter(0,
diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index 3b4d21e13..15454c3fe 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -84,15 +84,15 @@ class CheckerThreadContext : public ThreadContext
 
     int readCpuId() { return actualTC->readCpuId(); }
 
+    TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); }
+
+    TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); }
+
 #if FULL_SYSTEM
     System *getSystemPtr() { return actualTC->getSystemPtr(); }
 
     PhysicalMemory *getPhysMemPtr() { return actualTC->getPhysMemPtr(); }
 
-    TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); }
-
-    TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); }
-
     TheISA::Kernel::Statistics *getKernelStats()
     { return actualTC->getKernelStats(); }
 
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py
index e691cfe5d..27ca8ce1e 100644
--- a/src/cpu/o3/O3CPU.py
+++ b/src/cpu/o3/O3CPU.py
@@ -52,8 +52,8 @@ class DerivO3CPU(BaseCPU):
         else:
             checker = Param.BaseCPU(O3Checker(exitOnError=False, updateOnError=True,
                                               warnOnlyOnLoadError=False), "checker")
-            checker.itb = Parent.itb
-            checker.dtb = Parent.dtb
+        checker.itb = Parent.itb
+        checker.dtb = Parent.dtb
 
     cachePorts = Param.Unsigned(200, "Cache Ports")
     icache_port = Port("Instruction Port")
diff --git a/src/cpu/o3/alpha/cpu_builder.cc b/src/cpu/o3/alpha/cpu_builder.cc
index 4db217abf..1aa3d1618 100644
--- a/src/cpu/o3/alpha/cpu_builder.cc
+++ b/src/cpu/o3/alpha/cpu_builder.cc
@@ -77,10 +77,11 @@ DerivO3CPUParams::create()
     params->cpu_id = cpu_id;
     params->activity = activity;
 
-#if FULL_SYSTEM
-    params->system = system;
     params->itb = itb;
     params->dtb = dtb;
+
+#if FULL_SYSTEM
+    params->system = system;
     params->profile = profile;
 
     params->do_quiesce = do_quiesce;
diff --git a/src/cpu/o3/alpha/params.hh b/src/cpu/o3/alpha/params.hh
index b6b84b2a1..164c25312 100644
--- a/src/cpu/o3/alpha/params.hh
+++ b/src/cpu/o3/alpha/params.hh
@@ -54,10 +54,8 @@ class AlphaSimpleParams : public O3Params
 {
   public:
 
-#if FULL_SYSTEM
     AlphaISA::ITB *itb;
     AlphaISA::DTB *dtb;
-#endif
 };
 
 #endif // __CPU_O3_ALPHA_PARAMS_HH__
diff --git a/src/cpu/o3/checker_builder.cc b/src/cpu/o3/checker_builder.cc
index 97425b08c..0799b9cb5 100644
--- a/src/cpu/o3/checker_builder.cc
+++ b/src/cpu/o3/checker_builder.cc
@@ -86,9 +86,9 @@ O3CheckerParams::create()
     params->progress_interval = 0;
     temp2++;
 
-#if FULL_SYSTEM
     params->itb = itb;
     params->dtb = dtb;
+#if FULL_SYSTEM
     params->system = system;
     params->cpu_id = cpu_id;
     params->profile = profile;
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index cae6ae20c..98e200944 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -150,10 +150,8 @@ FullO3CPU<Impl>::DeallocateContextEvent::description()
 template <class Impl>
 FullO3CPU<Impl>::FullO3CPU(O3CPU *o3_cpu, Params *params)
     : BaseO3CPU(params),
-#if FULL_SYSTEM
       itb(params->itb),
       dtb(params->dtb),
-#endif
       tickEvent(this),
       removeInstsThisCycle(false),
       fetch(o3_cpu, params),
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 7d7e4e24d..d97a2080d 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -113,10 +113,8 @@ class FullO3CPU : public BaseO3CPU
         SwitchedOut
     };
 
-#if FULL_SYSTEM
     TheISA::ITB * itb;
     TheISA::DTB * dtb;
-#endif
 
     /** Overall CPU status. */
     Status _status;
@@ -265,7 +263,6 @@ class FullO3CPU : public BaseO3CPU
     /** Registers statistics. */
     void fullCPURegStats();
 
-#if FULL_SYSTEM
     /** Translates instruction requestion. */
     Fault translateInstReq(RequestPtr &req, Thread *thread)
     {
@@ -284,27 +281,6 @@ class FullO3CPU : public BaseO3CPU
         return this->dtb->translate(req, thread->getTC(), true);
     }
 
-#else
-    /** Translates instruction requestion in syscall emulation mode. */
-    Fault translateInstReq(RequestPtr &req, Thread *thread)
-    {
-        return thread->getProcessPtr()->pTable->translate(req);
-    }
-
-    /** Translates data read request in syscall emulation mode. */
-    Fault translateDataReadReq(RequestPtr &req, Thread *thread)
-    {
-        return thread->getProcessPtr()->pTable->translate(req);
-    }
-
-    /** Translates data write request in syscall emulation mode. */
-    Fault translateDataWriteReq(RequestPtr &req, Thread *thread)
-    {
-        return thread->getProcessPtr()->pTable->translate(req);
-    }
-
-#endif
-
     /** Returns a specific port. */
     Port *getPort(const std::string &if_name, int idx);
 
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 725baa1d0..043c65a4a 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -1226,7 +1226,6 @@ DefaultFetch<Impl>::fetch(bool &status_change)
         // Send the fault to commit.  This thread will not do anything
         // until commit handles the fault.  The only other way it can
         // wake up is if a squash comes along and changes the PC.
-#if FULL_SYSTEM
         assert(numInst < fetchWidth);
         // Get a sequence number.
         inst_seq = cpu->getAndIncrementInstSeq();
@@ -1258,11 +1257,7 @@ DefaultFetch<Impl>::fetch(bool &status_change)
 
         fetchStatus[tid] = TrapPending;
         status_change = true;
-#else // !FULL_SYSTEM
-        fetchStatus[tid] = TrapPending;
-        status_change = true;
 
-#endif // FULL_SYSTEM
         DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %08p",
                 tid, fault->name(), PC[tid]);
     }
diff --git a/src/cpu/o3/mips/params.hh b/src/cpu/o3/mips/params.hh
index d1ac62e21..2688d3fb3 100644
--- a/src/cpu/o3/mips/params.hh
+++ b/src/cpu/o3/mips/params.hh
@@ -36,8 +36,11 @@
 #include "cpu/o3/params.hh"
 
 //Forward declarations
-//class MipsDTB;
-//class MipsITB;
+namespace MipsISA
+{
+    class MipsDTB;
+    class MipsITB;
+}
 class MemObject;
 class Process;
 class System;
@@ -53,11 +56,9 @@ class MipsSimpleParams : public O3Params
   public:
     MipsSimpleParams() {}
 
-#if FULL_SYSTEM
     //Full System Paramater Objects place here
-    MipsITB *itb;
-    MipsDTB *dtb;
-#endif
+    MipsISA::ITB *itb;
+    MipsISA::DTB *dtb;
 };
 
 #endif // __CPU_O3_MIPS_PARAMS_HH__
diff --git a/src/cpu/o3/sparc/cpu_builder.cc b/src/cpu/o3/sparc/cpu_builder.cc
index 49f0f455d..b7c684431 100644
--- a/src/cpu/o3/sparc/cpu_builder.cc
+++ b/src/cpu/o3/sparc/cpu_builder.cc
@@ -78,10 +78,11 @@ DerivO3CPUParams::create()
     params->cpu_id = cpu_id;
     params->activity = activity;
 
-#if FULL_SYSTEM
-    params->system = system;
     params->itb = itb;
     params->dtb = dtb;
+
+#if FULL_SYSTEM
+    params->system = system;
     params->profile = profile;
 
     params->do_quiesce = do_quiesce;
diff --git a/src/cpu/o3/sparc/params.hh b/src/cpu/o3/sparc/params.hh
index d399d64c4..09f523818 100644
--- a/src/cpu/o3/sparc/params.hh
+++ b/src/cpu/o3/sparc/params.hh
@@ -54,10 +54,8 @@ class SparcSimpleParams : public O3Params
 {
   public:
 
-#if FULL_SYSTEM
     SparcISA::ITB *itb;
     SparcISA::DTB *dtb;
-#endif
 };
 
 #endif // __CPU_O3_SPARC_PARAMS_HH__
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 93638673b..31e08db4c 100755
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -66,13 +66,11 @@ class O3ThreadContext : public ThreadContext
     /** Pointer to the thread state that this TC corrseponds to. */
     O3ThreadState<Impl> *thread;
 
-#if FULL_SYSTEM
     /** Returns a pointer to the ITB. */
     TheISA::ITB *getITBPtr() { return cpu->itb; }
 
     /** Returns a pointer to the DTB. */
     TheISA::DTB *getDTBPtr() { return cpu->dtb; }
-#endif
 
     /** Returns a pointer to this CPU. */
     virtual BaseCPU *getCpuPtr() { return cpu; }
diff --git a/src/cpu/ozone/checker_builder.cc b/src/cpu/ozone/checker_builder.cc
index f813e5df2..625b2a39a 100644
--- a/src/cpu/ozone/checker_builder.cc
+++ b/src/cpu/ozone/checker_builder.cc
@@ -87,9 +87,9 @@ OzoneCheckerParams::create()
     temp2++;
     params->progress_interval = 0;
 
-#if FULL_SYSTEM
     params->itb = itb;
     params->dtb = dtb;
+#if FULL_SYSTEM
     params->system = system;
     params->cpu_id = cpu_id;
     params->profile = profile;
diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index 92b00af26..78d0892c4 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -120,15 +120,15 @@ class OzoneCPU : public BaseCPU
 
         int readCpuId() { return thread->readCpuId(); }
 
+        TheISA::ITB *getITBPtr() { return cpu->itb; }
+
+        TheISA::DTB * getDTBPtr() { return cpu->dtb; }
+
 #if FULL_SYSTEM
         System *getSystemPtr() { return cpu->system; }
 
         PhysicalMemory *getPhysMemPtr() { return cpu->physmem; }
 
-        TheISA::ITB *getITBPtr() { return cpu->itb; }
-
-        TheISA::DTB * getDTBPtr() { return cpu->dtb; }
-
         TheISA::Kernel::Statistics *getKernelStats()
         { return thread->getKernelStats(); }
 
diff --git a/src/cpu/ozone/cpu_builder.cc b/src/cpu/ozone/cpu_builder.cc
index 60ee9c4f9..7edbe41c9 100644
--- a/src/cpu/ozone/cpu_builder.cc
+++ b/src/cpu/ozone/cpu_builder.cc
@@ -79,11 +79,12 @@ DerivOzoneCPUParams::create()
     params->name = name;
     params->numberOfThreads = actual_num_threads;
 
+    params->itb = itb;
+    params->dtb = dtb;
+
 #if FULL_SYSTEM
     params->system = system;
     params->cpu_id = cpu_id;
-    params->itb = itb;
-    params->dtb = dtb;
     params->profile = profile;
     params->do_quiesce = do_quiesce;
     params->do_checkpoint_insts = do_checkpoint_insts;
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index d73e5768a..37a91c630 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -129,6 +129,8 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
     thread.inSyscall = false;
 
     thread.setStatus(ThreadContext::Suspended);
+    itb = p->itb;
+    dtb = p->dtb;
 #if FULL_SYSTEM
     // Setup thread state stuff.
     thread.cpu = this;
@@ -137,8 +139,6 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
     thread.quiesceEvent = new EndQuiesceEvent(tc);
 
     system = p->system;
-    itb = p->itb;
-    dtb = p->dtb;
     physmem = p->system->physmem;
 
     if (p->profile) {
diff --git a/src/cpu/ozone/simple_cpu_builder.cc b/src/cpu/ozone/simple_cpu_builder.cc
index df8e25fd0..ca55cdca4 100644
--- a/src/cpu/ozone/simple_cpu_builder.cc
+++ b/src/cpu/ozone/simple_cpu_builder.cc
@@ -82,11 +82,12 @@ SimpleOzoneCPUParams::create()
     params->name = name;
     params->numberOfThreads = actual_num_threads;
 
+    params->itb = itb;
+    params->dtb = dtb;
+
 #if FULL_SYSTEM
     params->system = system;
     params->cpu_id = cpu_id;
-    params->itb = itb;
-    params->dtb = dtb;
 #else
     params->workload = workload;
 //    params->pTable = page_table;
diff --git a/src/cpu/ozone/simple_params.hh b/src/cpu/ozone/simple_params.hh
index d5ba6a923..ec5782c8a 100644
--- a/src/cpu/ozone/simple_params.hh
+++ b/src/cpu/ozone/simple_params.hh
@@ -55,9 +55,8 @@ class SimpleParams : public BaseCPU::Params
 {
   public:
 
-#if FULL_SYSTEM
     TheISA::ITB *itb; TheISA::DTB *dtb;
-#else
+#if !FULL_SYSTEM
     std::vector<Process *> workload;
 #endif // FULL_SYSTEM
 
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index e2a7d5938..379c50b51 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -602,9 +602,9 @@ AtomicSimpleCPUParams::create()
     params->cpu_id = cpu_id;
     params->tracer = tracer;
 
-#if FULL_SYSTEM
     params->itb = itb;
     params->dtb = dtb;
+#if FULL_SYSTEM
     params->profile = profile;
     params->do_quiesce = do_quiesce;
     params->do_checkpoint_insts = do_checkpoint_insts;
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index d2dd52b64..aabaf1971 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -75,7 +75,7 @@ BaseSimpleCPU::BaseSimpleCPU(Params *p)
     thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
 #else
     thread = new SimpleThread(this, /* thread_num */ 0, p->process,
-            /* asid */ 0);
+            p->itb, p->dtb, /* asid */ 0);
 #endif // !FULL_SYSTEM
 
     thread->setStatus(ThreadContext::Unallocated);
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 22ffff3b9..843fd025c 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -100,10 +100,9 @@ class BaseSimpleCPU : public BaseCPU
   public:
     struct Params : public BaseCPU::Params
     {
-#if FULL_SYSTEM
         TheISA::ITB *itb;
         TheISA::DTB *dtb;
-#else
+#if !FULL_SYSTEM
         Process *process;
 #endif
     };
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index a70ca7c75..70b774deb 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -727,9 +727,9 @@ TimingSimpleCPUParams::create()
     params->cpu_id = cpu_id;
     params->tracer = tracer;
 
-#if FULL_SYSTEM
     params->itb = itb;
     params->dtb = dtb;
+#if FULL_SYSTEM
     params->profile = profile;
     params->do_quiesce = do_quiesce;
     params->do_checkpoint_insts = do_checkpoint_insts;
diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index 191ae2f2e..93772fbe1 100644
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -93,10 +93,10 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
     }
 }
 #else
-SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num,
-                         Process *_process, int _asid)
+SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
+                           TheISA::ITB *_itb, TheISA::DTB *_dtb, int _asid)
     : ThreadState(_cpu, -1, _thread_num, _process, _asid),
-      cpu(_cpu)
+      cpu(_cpu), itb(_itb), dtb(_dtb)
 {
     regs.clear();
     tc = new ProxyThreadContext<SimpleThread>(this);
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 6c6d5f842..1e87b0bb7 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -35,6 +35,7 @@
 #include "arch/isa_traits.hh"
 #include "arch/regfile.hh"
 #include "arch/syscallreturn.hh"
+#include "arch/tlb.hh"
 #include "config/full_system.hh"
 #include "cpu/thread_context.hh"
 #include "cpu/thread_state.hh"
@@ -49,7 +50,6 @@ class BaseCPU;
 #if FULL_SYSTEM
 
 #include "sim/system.hh"
-#include "arch/tlb.hh"
 
 class FunctionProfile;
 class ProfileNode;
@@ -109,10 +109,8 @@ class SimpleThread : public ThreadState
 
     System *system;
 
-#if FULL_SYSTEM
     TheISA::ITB *itb;
     TheISA::DTB *dtb;
-#endif
 
     // constructor: initialize SimpleThread from given process structure
 #if FULL_SYSTEM
@@ -120,7 +118,8 @@ class SimpleThread : public ThreadState
                  TheISA::ITB *_itb, TheISA::DTB *_dtb,
                  bool use_kernel_stats = true);
 #else
-    SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid);
+    SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
+                 TheISA::ITB *_itb, TheISA::DTB *_dtb, int _asid);
 #endif
 
     SimpleThread();
@@ -149,10 +148,6 @@ class SimpleThread : public ThreadState
      */
     ThreadContext *getTC() { return tc; }
 
-#if FULL_SYSTEM
-    int getInstAsid() { return regs.instAsid(); }
-    int getDataAsid() { return regs.dataAsid(); }
-
     Fault translateInstReq(RequestPtr &req)
     {
         return itb->translate(req, tc);
@@ -168,27 +163,16 @@ class SimpleThread : public ThreadState
         return dtb->translate(req, tc, true);
     }
 
+#if FULL_SYSTEM
+    int getInstAsid() { return regs.instAsid(); }
+    int getDataAsid() { return regs.dataAsid(); }
+
     void dumpFuncProfile();
 
     Fault hwrei();
 
     bool simPalCheck(int palFunc);
-#else
-
-    Fault translateInstReq(RequestPtr &req)
-    {
-        return process->pTable->translate(req);
-    }
-
-    Fault translateDataReadReq(RequestPtr &req)
-    {
-        return process->pTable->translate(req);
-    }
 
-    Fault translateDataWriteReq(RequestPtr &req)
-    {
-        return process->pTable->translate(req);
-    }
 #endif
 
     /*******************************************
@@ -199,13 +183,13 @@ class SimpleThread : public ThreadState
 
     int getThreadNum() { return tid; }
 
-#if FULL_SYSTEM
-    System *getSystemPtr() { return system; }
-
     TheISA::ITB *getITBPtr() { return itb; }
 
     TheISA::DTB *getDTBPtr() { return dtb; }
 
+#if FULL_SYSTEM
+    System *getSystemPtr() { return system; }
+
     FunctionalPort *getPhysPort() { return physPort; }
 
     /** Return a virtual port. If no thread context is specified then a static
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 3706d8543..1af029093 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -119,13 +119,13 @@ class ThreadContext
 
     virtual int readCpuId() = 0;
 
-#if FULL_SYSTEM
-    virtual System *getSystemPtr() = 0;
-
     virtual TheISA::ITB *getITBPtr() = 0;
 
     virtual TheISA::DTB *getDTBPtr() = 0;
 
+#if FULL_SYSTEM
+    virtual System *getSystemPtr() = 0;
+
     virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
 
     virtual FunctionalPort *getPhysPort() = 0;
@@ -298,13 +298,13 @@ class ProxyThreadContext : public ThreadContext
 
     int readCpuId() { return actualTC->readCpuId(); }
 
-#if FULL_SYSTEM
-    System *getSystemPtr() { return actualTC->getSystemPtr(); }
-
     TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); }
 
     TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); }
 
+#if FULL_SYSTEM
+    System *getSystemPtr() { return actualTC->getSystemPtr(); }
+
     TheISA::Kernel::Statistics *getKernelStats()
     { return actualTC->getKernelStats(); }