stats: rename stats so they can be used as python expressions

8 files changed, 101 insertions, 90 deletions

diff --git a/src/cpu/inorder/pipeline_stage.cc b/src/cpu/inorder/pipeline_stage.cc
index fe97fb8f4..51e16b6c4 100644
--- a/src/cpu/inorder/pipeline_stage.cc
+++ b/src/cpu/inorder/pipeline_stage.cc
@@ -88,7 +88,7 @@ PipelineStage::init(Params *params)
 std::string
 PipelineStage::name() const
 {
-     return cpu->name() + ".stage-" + to_string(stageNum);
+     return cpu->name() + ".stage" + to_string(stageNum);
 }
 
 
diff --git a/src/cpu/inorder/resource_pool.9stage.cc b/src/cpu/inorder/resource_pool.9stage.cc
index 93b0ac4e4..78a7d4b88 100644
--- a/src/cpu/inorder/resource_pool.9stage.cc
+++ b/src/cpu/inorder/resource_pool.9stage.cc
@@ -48,37 +48,48 @@ ResourcePool::ResourcePool(InOrderCPU *_cpu, InOrderCPUParams *params)
     // Declare Resource Objects
     // name - id - bandwidth - latency - CPU - Parameters
     // --------------------------------------------------
-    resources.push_back(new FetchSeqUnit("Fetch-Seq-Unit", FetchSeq, StageWidth * 2, 0, _cpu, params));
+    resources.push_back(new FetchSeqUnit("fetch_seq_unit", FetchSeq,
+            StageWidth * 2, 0, _cpu, params));
 
-    resources.push_back(new TLBUnit("I-TLB", ITLB, StageWidth, 0, _cpu, params));
+    resources.push_back(new TLBUnit("itlb", ITLB, StageWidth, 0, _cpu, params));
 
     memObjects.push_back(ICache);
-    resources.push_back(new CacheUnit("icache_port", ICache, StageWidth * MaxThreads, 0, _cpu, params));
+    resources.push_back(new CacheUnit("icache_port", ICache,
+            StageWidth * MaxThreads, 0, _cpu, params));
 
-    resources.push_back(new DecodeUnit("Decode-Unit", Decode, StageWidth, 0, _cpu, params));
+    resources.push_back(new DecodeUnit("decode_unit", Decode, StageWidth, 0,
+            _cpu, params));
 
-    resources.push_back(new BranchPredictor("Branch-Predictor", BPred, StageWidth, 0, _cpu, params));
+    resources.push_back(new BranchPredictor("branch_predictor", BPred,
+            StageWidth, 0, _cpu, params));
 
     for (int i = 0; i < params->numberOfThreads; i++) {
         char fbuff_name[20];
-        sprintf(fbuff_name, "Fetch-Buffer-T%i", i);
-        resources.push_back(new InstBuffer(fbuff_name, FetchBuff + i, 4, 0, _cpu, params));
+        sprintf(fbuff_name, "fetch_buffer_t%i", i);
+        resources.push_back(new InstBuffer(fbuff_name, FetchBuff + i, 4, 0,
+                _cpu, params));
     }
 
-    resources.push_back(new UseDefUnit("RegFile-Manager", RegManager, StageWidth * MaxThreads, 0, _cpu, params));
+    resources.push_back(new UseDefUnit("regfile_manager", RegManager,
+            StageWidth * MaxThreads, 0, _cpu, params));
 
-    resources.push_back(new AGENUnit("AGEN-Unit", AGEN, StageWidth, 0, _cpu, params));
+    resources.push_back(new AGENUnit("agen_unit", AGEN, StageWidth, 0, _cpu,
+            params));
 
-    resources.push_back(new ExecutionUnit("Execution-Unit", ExecUnit, StageWidth, 0, _cpu, params));
+    resources.push_back(new ExecutionUnit("execution_unit", ExecUnit,
+            StageWidth, 0, _cpu, params));
 
-    resources.push_back(new MultDivUnit("Mult-Div-Unit", MDU, 5, 0, _cpu, params));
+    resources.push_back(new MultDivUnit("mult_div_unit", MDU, 5, 0, _cpu,
+            params));
 
-    resources.push_back(new TLBUnit("D-TLB", DTLB, StageWidth, 0, _cpu, params));
+    resources.push_back(new TLBUnit("dtlb", DTLB, StageWidth, 0, _cpu, params));
 
     memObjects.push_back(DCache);
-    resources.push_back(new CacheUnit("dcache_port", DCache, StageWidth * MaxThreads, 0, _cpu, params));
+    resources.push_back(new CacheUnit("dcache_port", DCache,
+            StageWidth * MaxThreads, 0, _cpu, params));
 
-    resources.push_back(new GraduationUnit("Graduation-Unit", Grad, StageWidth * MaxThreads, 0, _cpu, params));
+    resources.push_back(new GraduationUnit("graduation_unit", Grad,
+            StageWidth * MaxThreads, 0, _cpu, params));
 }
 
 void
diff --git a/src/cpu/inorder/resource_pool.cc b/src/cpu/inorder/resource_pool.cc
index 536a3b53c..263512611 100644
--- a/src/cpu/inorder/resource_pool.cc
+++ b/src/cpu/inorder/resource_pool.cc
@@ -51,7 +51,7 @@ ResourcePool::ResourcePool(InOrderCPU *_cpu, ThePipeline::Params *params)
     // Declare Resource Objects
     // name - id - bandwidth - latency - CPU - Parameters
     // --------------------------------------------------
-    resources.push_back(new FetchSeqUnit("Fetch-Seq-Unit", FetchSeq, 
+    resources.push_back(new FetchSeqUnit("fetch_seq_unit", FetchSeq,
                                          stage_width * 2, 0, _cpu, params));
 
     memObjects.push_back(ICache);
@@ -59,26 +59,26 @@ ResourcePool::ResourcePool(InOrderCPU *_cpu, ThePipeline::Params *params)
                                       stage_width * 2 + MaxThreads, 0, _cpu,
                                       params));
 
-    resources.push_back(new DecodeUnit("Decode-Unit", Decode, 
+    resources.push_back(new DecodeUnit("decode_unit", Decode,
                                        stage_width, 0, _cpu, params));
 
-    resources.push_back(new BranchPredictor("Branch-Predictor", BPred, 
+    resources.push_back(new BranchPredictor("branch_predictor", BPred,
                                             stage_width, 0, _cpu, params));
 
-    resources.push_back(new InstBuffer("Fetch-Buffer-T0", FetchBuff, 4, 
+    resources.push_back(new InstBuffer("fetch_buffer_t0", FetchBuff, 4,
                                        0, _cpu, params));
 
-    resources.push_back(new UseDefUnit("RegFile-Manager", RegManager, 
+    resources.push_back(new UseDefUnit("regfile_manager", RegManager,
                                        stage_width * 3, 0, _cpu,
                                        params));
 
-    resources.push_back(new AGENUnit("AGEN-Unit", AGEN, 
+    resources.push_back(new AGENUnit("agen_unit", AGEN,
                                      stage_width, 0, _cpu, params));
 
-    resources.push_back(new ExecutionUnit("Execution-Unit", ExecUnit, 
+    resources.push_back(new ExecutionUnit("execution_unit", ExecUnit,
                                           stage_width, 0, _cpu, params));
 
-    resources.push_back(new MultDivUnit("Mult-Div-Unit", MDU,
+    resources.push_back(new MultDivUnit("mult_div_unit", MDU,
                                         stage_width * 2, 0, _cpu, params));
 
     memObjects.push_back(DCache);
@@ -86,11 +86,11 @@ ResourcePool::ResourcePool(InOrderCPU *_cpu, ThePipeline::Params *params)
                                       stage_width * 2 + MaxThreads, 0, _cpu,
                                       params));
 
-    resources.push_back(new GraduationUnit("Graduation-Unit", Grad, 
+    resources.push_back(new GraduationUnit("graduation_unit", Grad,
                                            stage_width, 0, _cpu,
                                            params));
 
-    resources.push_back(new InstBuffer("Fetch-Buffer-T1", FetchBuff2, 4, 
+    resources.push_back(new InstBuffer("fetch_buffer_t1", FetchBuff2, 4,
                                        0, _cpu, params));
 
 }
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index aa72c0750..9e7dd65df 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -188,83 +188,83 @@ DefaultCommit<Impl>::regStats()
         .prereq(branchMispredicts);
     numCommittedDist
         .init(0,commitWidth,1)
-        .name(name() + ".COM:committed_per_cycle")
+        .name(name() + ".committed_per_cycle")
         .desc("Number of insts commited each cycle")
         .flags(Stats::pdf)
         ;
 
     statComInst
         .init(cpu->numThreads)
-        .name(name() + ".COM:count")
+        .name(name() + ".count")
         .desc("Number of instructions committed")
         .flags(total)
         ;
 
     statComSwp
         .init(cpu->numThreads)
-        .name(name() + ".COM:swp_count")
+        .name(name() + ".swp_count")
         .desc("Number of s/w prefetches committed")
         .flags(total)
         ;
 
     statComRefs
         .init(cpu->numThreads)
-        .name(name() +  ".COM:refs")
+        .name(name() +  ".refs")
         .desc("Number of memory references committed")
         .flags(total)
         ;
 
     statComLoads
         .init(cpu->numThreads)
-        .name(name() +  ".COM:loads")
+        .name(name() +  ".loads")
         .desc("Number of loads committed")
         .flags(total)
         ;
 
     statComMembars
         .init(cpu->numThreads)
-        .name(name() +  ".COM:membars")
+        .name(name() +  ".membars")
         .desc("Number of memory barriers committed")
         .flags(total)
         ;
 
     statComBranches
         .init(cpu->numThreads)
-        .name(name() + ".COM:branches")
+        .name(name() + ".branches")
         .desc("Number of branches committed")
         .flags(total)
         ;
 
     statComFloating
         .init(cpu->numThreads)
-        .name(name() + ".COM:fp_insts")
+        .name(name() + ".fp_insts")
         .desc("Number of committed floating point instructions.")
         .flags(total)
         ;
 
     statComInteger
         .init(cpu->numThreads)
-        .name(name()+".COM:int_insts")
+        .name(name()+".int_insts")
         .desc("Number of committed integer instructions.")
         .flags(total)
         ;
 
     statComFunctionCalls
         .init(cpu->numThreads)
-        .name(name()+".COM:function_calls")
+        .name(name()+".function_calls")
         .desc("Number of function calls committed.")
         .flags(total)
         ;
 
     commitEligible
         .init(cpu->numThreads)
-        .name(name() + ".COM:bw_limited")
+        .name(name() + ".bw_limited")
         .desc("number of insts not committed due to BW limits")
         .flags(total)
         ;
 
     commitEligibleSamples
-        .name(name() + ".COM:bw_lim_events")
+        .name(name() + ".bw_lim_events")
         .desc("number cycles where commit BW limit reached")
         ;
 }
diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh
index 010dbfa5a..4beabbc02 100644
--- a/src/cpu/o3/decode_impl.hh
+++ b/src/cpu/o3/decode_impl.hh
@@ -77,44 +77,44 @@ void
 DefaultDecode<Impl>::regStats()
 {
     decodeIdleCycles
-        .name(name() + ".DECODE:IdleCycles")
+        .name(name() + ".IdleCycles")
         .desc("Number of cycles decode is idle")
         .prereq(decodeIdleCycles);
     decodeBlockedCycles
-        .name(name() + ".DECODE:BlockedCycles")
+        .name(name() + ".BlockedCycles")
         .desc("Number of cycles decode is blocked")
         .prereq(decodeBlockedCycles);
     decodeRunCycles
-        .name(name() + ".DECODE:RunCycles")
+        .name(name() + ".RunCycles")
         .desc("Number of cycles decode is running")
         .prereq(decodeRunCycles);
     decodeUnblockCycles
-        .name(name() + ".DECODE:UnblockCycles")
+        .name(name() + ".UnblockCycles")
         .desc("Number of cycles decode is unblocking")
         .prereq(decodeUnblockCycles);
     decodeSquashCycles
-        .name(name() + ".DECODE:SquashCycles")
+        .name(name() + ".SquashCycles")
         .desc("Number of cycles decode is squashing")
         .prereq(decodeSquashCycles);
     decodeBranchResolved
-        .name(name() + ".DECODE:BranchResolved")
+        .name(name() + ".BranchResolved")
         .desc("Number of times decode resolved a branch")
         .prereq(decodeBranchResolved);
     decodeBranchMispred
-        .name(name() + ".DECODE:BranchMispred")
+        .name(name() + ".BranchMispred")
         .desc("Number of times decode detected a branch misprediction")
         .prereq(decodeBranchMispred);
     decodeControlMispred
-        .name(name() + ".DECODE:ControlMispred")
+        .name(name() + ".ControlMispred")
         .desc("Number of times decode detected an instruction incorrectly"
               " predicted as a control")
         .prereq(decodeControlMispred);
     decodeDecodedInsts
-        .name(name() + ".DECODE:DecodedInsts")
+        .name(name() + ".DecodedInsts")
         .desc("Number of instructions handled by decode")
         .prereq(decodeDecodedInsts);
     decodeSquashedInsts
-        .name(name() + ".DECODE:SquashedInsts")
+        .name(name() + ".SquashedInsts")
         .desc("Number of squashed instructions handled by decode")
         .prereq(decodeSquashedInsts);
 }
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index 2569dbb34..23f551ee3 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -194,36 +194,36 @@ DefaultIEW<Impl>::regStats()
 
     iewExecutedSwp
         .init(cpu->numThreads)
-        .name(name() + ".EXEC:swp")
+        .name(name() + ".exec_swp")
         .desc("number of swp insts executed")
         .flags(total);
 
     iewExecutedNop
         .init(cpu->numThreads)
-        .name(name() + ".EXEC:nop")
+        .name(name() + ".exec_nop")
         .desc("number of nop insts executed")
         .flags(total);
 
     iewExecutedRefs
         .init(cpu->numThreads)
-        .name(name() + ".EXEC:refs")
+        .name(name() + ".exec_refs")
         .desc("number of memory reference insts executed")
         .flags(total);
 
     iewExecutedBranches
         .init(cpu->numThreads)
-        .name(name() + ".EXEC:branches")
+        .name(name() + ".exec_branches")
         .desc("Number of branches executed")
         .flags(total);
 
     iewExecStoreInsts
-        .name(name() + ".EXEC:stores")
+        .name(name() + ".exec_stores")
         .desc("Number of stores executed")
         .flags(total);
     iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts;
 
     iewExecRate
-        .name(name() + ".EXEC:rate")
+        .name(name() + ".exec_rate")
         .desc("Inst execution rate")
         .flags(total);
 
@@ -231,50 +231,50 @@ DefaultIEW<Impl>::regStats()
 
     iewInstsToCommit
         .init(cpu->numThreads)
-        .name(name() + ".WB:sent")
+        .name(name() + ".wb_sent")
         .desc("cumulative count of insts sent to commit")
         .flags(total);
 
     writebackCount
         .init(cpu->numThreads)
-        .name(name() + ".WB:count")
+        .name(name() + ".wb_count")
         .desc("cumulative count of insts written-back")
         .flags(total);
 
     producerInst
         .init(cpu->numThreads)
-        .name(name() + ".WB:producers")
+        .name(name() + ".wb_producers")
         .desc("num instructions producing a value")
         .flags(total);
 
     consumerInst
         .init(cpu->numThreads)
-        .name(name() + ".WB:consumers")
+        .name(name() + ".wb_consumers")
         .desc("num instructions consuming a value")
         .flags(total);
 
     wbPenalized
         .init(cpu->numThreads)
-        .name(name() + ".WB:penalized")
+        .name(name() + ".wb_penalized")
         .desc("number of instrctions required to write to 'other' IQ")
         .flags(total);
 
     wbPenalizedRate
-        .name(name() + ".WB:penalized_rate")
+        .name(name() + ".wb_penalized_rate")
         .desc ("fraction of instructions written-back that wrote to 'other' IQ")
         .flags(total);
 
     wbPenalizedRate = wbPenalized / writebackCount;
 
     wbFanout
-        .name(name() + ".WB:fanout")
+        .name(name() + ".wb_fanout")
         .desc("average fanout of values written-back")
         .flags(total);
 
     wbFanout = producerInst / consumerInst;
 
     wbRate
-        .name(name() + ".WB:rate")
+        .name(name() + ".wb_rate")
         .desc("insts written-back per cycle")
         .flags(total);
     wbRate = writebackCount / cpu->numCycles;
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index bac9e2ec6..8592cd6b1 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -258,14 +258,14 @@ InstructionQueue<Impl>::regStats()
 */
     numIssuedDist
         .init(0,totalWidth,1)
-        .name(name() + ".ISSUE:issued_per_cycle")
+        .name(name() + ".issued_per_cycle")
         .desc("Number of insts issued each cycle")
         .flags(pdf)
         ;
 /*
     dist_unissued
         .init(Num_OpClasses+2)
-        .name(name() + ".ISSUE:unissued_cause")
+        .name(name() + ".unissued_cause")
         .desc("Reason ready instruction not issued")
         .flags(pdf | dist)
         ;
@@ -275,7 +275,7 @@ InstructionQueue<Impl>::regStats()
 */
     statIssuedInstType
         .init(numThreads,Enums::Num_OpClass)
-        .name(name() + ".ISSUE:FU_type")
+        .name(name() + ".FU_type")
         .desc("Type of FU issued")
         .flags(total | pdf | dist)
         ;
@@ -287,7 +287,7 @@ InstructionQueue<Impl>::regStats()
 /*
     issueDelayDist
         .init(Num_OpClasses,0,99,2)
-        .name(name() + ".ISSUE:")
+        .name(name() + ".")
         .desc("cycles from operands ready to issue")
         .flags(pdf | cdf)
         ;
@@ -299,7 +299,7 @@ InstructionQueue<Impl>::regStats()
     }
 */
     issueRate
-        .name(name() + ".ISSUE:rate")
+        .name(name() + ".rate")
         .desc("Inst issue rate")
         .flags(total)
         ;
@@ -307,7 +307,7 @@ InstructionQueue<Impl>::regStats()
 
     statFuBusy
         .init(Num_OpClasses)
-        .name(name() + ".ISSUE:fu_full")
+        .name(name() + ".fu_full")
         .desc("attempts to use FU when none available")
         .flags(pdf | dist)
         ;
@@ -317,13 +317,13 @@ InstructionQueue<Impl>::regStats()
 
     fuBusy
         .init(numThreads)
-        .name(name() + ".ISSUE:fu_busy_cnt")
+        .name(name() + ".fu_busy_cnt")
         .desc("FU busy when requested")
         .flags(total)
         ;
 
     fuBusyRate
-        .name(name() + ".ISSUE:fu_busy_rate")
+        .name(name() + ".fu_busy_rate")
         .desc("FU busy rate (busy events/executed inst)")
         .flags(total)
         ;
diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index 7d20cac30..25f77ea82 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -103,90 +103,90 @@ void
 DefaultRename<Impl>::regStats()
 {
     renameSquashCycles
-        .name(name() + ".RENAME:SquashCycles")
+        .name(name() + ".SquashCycles")
         .desc("Number of cycles rename is squashing")
         .prereq(renameSquashCycles);
     renameIdleCycles
-        .name(name() + ".RENAME:IdleCycles")
+        .name(name() + ".IdleCycles")
         .desc("Number of cycles rename is idle")
         .prereq(renameIdleCycles);
     renameBlockCycles
-        .name(name() + ".RENAME:BlockCycles")
+        .name(name() + ".BlockCycles")
         .desc("Number of cycles rename is blocking")
         .prereq(renameBlockCycles);
     renameSerializeStallCycles
-        .name(name() + ".RENAME:serializeStallCycles")
+        .name(name() + ".serializeStallCycles")
         .desc("count of cycles rename stalled for serializing inst")
         .flags(Stats::total);
     renameRunCycles
-        .name(name() + ".RENAME:RunCycles")
+        .name(name() + ".RunCycles")
         .desc("Number of cycles rename is running")
         .prereq(renameIdleCycles);
     renameUnblockCycles
-        .name(name() + ".RENAME:UnblockCycles")
+        .name(name() + ".UnblockCycles")
         .desc("Number of cycles rename is unblocking")
         .prereq(renameUnblockCycles);
     renameRenamedInsts
-        .name(name() + ".RENAME:RenamedInsts")
+        .name(name() + ".RenamedInsts")
         .desc("Number of instructions processed by rename")
         .prereq(renameRenamedInsts);
     renameSquashedInsts
-        .name(name() + ".RENAME:SquashedInsts")
+        .name(name() + ".SquashedInsts")
         .desc("Number of squashed instructions processed by rename")
         .prereq(renameSquashedInsts);
     renameROBFullEvents
-        .name(name() + ".RENAME:ROBFullEvents")
+        .name(name() + ".ROBFullEvents")
         .desc("Number of times rename has blocked due to ROB full")
         .prereq(renameROBFullEvents);
     renameIQFullEvents
-        .name(name() + ".RENAME:IQFullEvents")
+        .name(name() + ".IQFullEvents")
         .desc("Number of times rename has blocked due to IQ full")
         .prereq(renameIQFullEvents);
     renameLSQFullEvents
-        .name(name() + ".RENAME:LSQFullEvents")
+        .name(name() + ".LSQFullEvents")
         .desc("Number of times rename has blocked due to LSQ full")
         .prereq(renameLSQFullEvents);
     renameFullRegistersEvents
-        .name(name() + ".RENAME:FullRegisterEvents")
+        .name(name() + ".FullRegisterEvents")
         .desc("Number of times there has been no free registers")
         .prereq(renameFullRegistersEvents);
     renameRenamedOperands
-        .name(name() + ".RENAME:RenamedOperands")
+        .name(name() + ".RenamedOperands")
         .desc("Number of destination operands rename has renamed")
         .prereq(renameRenamedOperands);
     renameRenameLookups
-        .name(name() + ".RENAME:RenameLookups")
+        .name(name() + ".RenameLookups")
         .desc("Number of register rename lookups that rename has made")
         .prereq(renameRenameLookups);
     renameCommittedMaps
-        .name(name() + ".RENAME:CommittedMaps")
+        .name(name() + ".CommittedMaps")
         .desc("Number of HB maps that are committed")
         .prereq(renameCommittedMaps);
     renameUndoneMaps
-        .name(name() + ".RENAME:UndoneMaps")
+        .name(name() + ".UndoneMaps")
         .desc("Number of HB maps that are undone due to squashing")
         .prereq(renameUndoneMaps);
     renamedSerializing
-        .name(name() + ".RENAME:serializingInsts")
+        .name(name() + ".serializingInsts")
         .desc("count of serializing insts renamed")
         .flags(Stats::total)
         ;
     renamedTempSerializing
-        .name(name() + ".RENAME:tempSerializingInsts")
+        .name(name() + ".tempSerializingInsts")
         .desc("count of temporary serializing insts renamed")
         .flags(Stats::total)
         ;
     renameSkidInsts
-        .name(name() + ".RENAME:skidInsts")
+        .name(name() + ".skidInsts")
         .desc("count of insts added to the skid buffer")
         .flags(Stats::total)
         ;
     intRenameLookups
-        .name(name() + ".RENAME:int_rename_lookups")
+        .name(name() + ".int_rename_lookups")
         .desc("Number of integer rename lookups")
         .prereq(intRenameLookups);
     fpRenameLookups
-        .name(name() + ".RENAME:fp_rename_lookups")
+        .name(name() + ".fp_rename_lookups")
         .desc("Number of floating rename lookups")
         .prereq(fpRenameLookups);
 }