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authorMin Kyu Jeong <minkyu.jeong@arm.com>2010-08-23 11:18:41 -0500
committerMin Kyu Jeong <minkyu.jeong@arm.com>2010-08-23 11:18:41 -0500
commit92ae620be8b46742042dcfe6dfaf38ecac24ad09 (patch)
tree740b871d75a40aa85582ba11aadca144978f2378 /src/cpu
parent43c938d23e2b28c7190bd10c470c452676f5cb9d (diff)
downloadgem5-92ae620be8b46742042dcfe6dfaf38ecac24ad09.tar.xz
ARM: mark msr/mrs instructions as SerializeBefore/After
Since miscellaneous registers bypass wakeup logic, force serialization to resolve data dependencies through them * * * ARM: adding non-speculative/serialize flags for instructions change CPSR
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/base_dyn_inst_impl.hh2
-rw-r--r--src/cpu/o3/iew_impl.hh1
-rw-r--r--src/cpu/o3/inst_queue_impl.hh6
3 files changed, 7 insertions, 2 deletions
diff --git a/src/cpu/base_dyn_inst_impl.hh b/src/cpu/base_dyn_inst_impl.hh
index 7425431db..4fb8490c1 100644
--- a/src/cpu/base_dyn_inst_impl.hh
+++ b/src/cpu/base_dyn_inst_impl.hh
@@ -321,6 +321,8 @@ template <class Impl>
void
BaseDynInst<Impl>::markSrcRegReady()
{
+ DPRINTF(IQ, "[sn:%lli] has %d ready out of %d sources. RTI %d)\n",
+ seqNum, readyRegs+1, numSrcRegs(), readyToIssue());
if (++readyRegs == numSrcRegs()) {
setCanIssue();
}
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index b53b03fe0..abb941ef7 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -1192,6 +1192,7 @@ DefaultIEW<Impl>::executeInsts()
}
// Uncomment this if you want to see all available instructions.
+ // @todo This doesn't actually work anymore, we should fix it.
// printAvailableInsts();
// Execute/writeback any instructions that are available.
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index b6d1ec8b0..3d5eadf84 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -896,6 +896,8 @@ InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst)
// handled by the IQ and thus have no dependency graph entry.
// @todo Figure out a cleaner way to handle this.
if (dest_reg >= numPhysRegs) {
+ DPRINTF(IQ, "dest_reg :%d, numPhysRegs: %d\n", dest_reg,
+ numPhysRegs);
continue;
}
@@ -907,8 +909,8 @@ InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst)
DynInstPtr dep_inst = dependGraph.pop(dest_reg);
while (dep_inst) {
- DPRINTF(IQ, "Waking up a dependent instruction, PC%#x.\n",
- dep_inst->readPC());
+ DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] "
+ "PC%#x.\n", dep_inst->seqNum, dep_inst->readPC());
// Might want to give more information to the instruction
// so that it knows which of its source registers is