Merge zizzer.eecs.umich.edu:/bk/newmem

into  doughnut.mwconnections.com:/home/gblack/m5/newmem-x86

--HG--
extra : convert_revision : 3f17fc418ee5a30da2b08a515fb394cc8fcdd237

8 files changed, 32 insertions, 24 deletions

diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 65625065d..dd4c333d3 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -641,9 +641,6 @@ DefaultCommit<Impl>::handleInterrupt()
             // an interrupt needed to be handled.
             DPRINTF(Commit, "Interrupt detected.\n");
 
-            Fault new_interrupt = cpu->getInterrupts();
-            assert(new_interrupt != NoFault);
-
             // Clear the interrupt now that it's going to be handled
             toIEW->commitInfo[0].clearInterrupt = true;
 
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 2e6a43f9c..a775b66d5 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -384,25 +384,25 @@ FullO3CPU<Impl>::fullCPURegStats()
         .name(name() + ".cpi")
         .desc("CPI: Cycles Per Instruction")
         .precision(6);
-    cpi = simTicks / committedInsts;
+    cpi = numCycles / committedInsts;
 
     totalCpi
         .name(name() + ".cpi_total")
         .desc("CPI: Total CPI of All Threads")
         .precision(6);
-    totalCpi = simTicks / totalCommittedInsts;
+    totalCpi = numCycles / totalCommittedInsts;
 
     ipc
         .name(name() + ".ipc")
         .desc("IPC: Instructions Per Cycle")
         .precision(6);
-    ipc =  committedInsts / simTicks;
+    ipc =  committedInsts / numCycles;
 
     totalIpc
         .name(name() + ".ipc_total")
         .desc("IPC: Total IPC of All Threads")
         .precision(6);
-    totalIpc =  totalCommittedInsts / simTicks;
+    totalIpc =  totalCommittedInsts / numCycles;
 
 }
 
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index f24de20d9..cc33e025d 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -33,6 +33,7 @@
 #define __CPU_O3_LSQ_UNIT_HH__
 
 #include <algorithm>
+#include <cstring>
 #include <map>
 #include <queue>
 
@@ -292,7 +293,7 @@ class LSQUnit {
             : inst(NULL), req(NULL), size(0),
               canWB(0), committed(0), completed(0)
         {
-            bzero(data, sizeof(data));
+            std::memset(data, 0, sizeof(data));
         }
 
         /** Constructs a store queue entry for a given instruction. */
@@ -300,7 +301,7 @@ class LSQUnit {
             : inst(_inst), req(NULL), size(0),
               canWB(0), committed(0), completed(0)
         {
-            bzero(data, sizeof(data));
+            std::memset(data, 0, sizeof(data));
         }
 
         /** The store instruction. */
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 44e2cea76..bde4f8079 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -680,7 +680,6 @@ LSQUnit<Impl>::writebackStores()
                         inst->seqNum);
                 WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this);
                 wb->schedule(curTick + 1);
-                delete state;
                 completeStore(storeWBIdx);
                 incrStIdx(storeWBIdx);
                 continue;
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 4f623a3f5..d2718c5f9 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -79,7 +79,7 @@ BaseSimpleCPU::BaseSimpleCPU(Params *p)
             /* asid */ 0);
 #endif // !FULL_SYSTEM
 
-    thread->setStatus(ThreadContext::Suspended);
+    thread->setStatus(ThreadContext::Unallocated);
 
     tc = thread->getTC();
 
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 45da7c3eb..fa7bb4f86 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -574,10 +574,16 @@ TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
 
         return true;
     }
-    else {
-        //Snooping a Coherence Request, do nothing
-        return true;
+    else if (pkt->result == Packet::Nacked) {
+        assert(cpu->_status == IcacheWaitResponse);
+        pkt->reinitNacked();
+        if (!sendTiming(pkt)) {
+            cpu->_status = IcacheRetry;
+            cpu->ifetch_pkt = pkt;
+        }
     }
+    //Snooping a Coherence Request, do nothing
+    return true;
 }
 
 void
@@ -663,10 +669,16 @@ TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
 
         return true;
     }
-    else {
-        //Snooping a coherence req, do nothing
-        return true;
+    else if (pkt->result == Packet::Nacked) {
+        assert(cpu->_status == DcacheWaitResponse);
+        pkt->reinitNacked();
+        if (!sendTiming(pkt)) {
+            cpu->_status = DcacheRetry;
+            cpu->dcache_pkt = pkt;
+        }
     }
+    //Snooping a Coherence Request, do nothing
+    return true;
 }
 
 void
diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index 39f31782b..191ae2f2e 100644
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -221,10 +221,10 @@ SimpleThread::activate(int delay)
 
     lastActivate = curTick;
 
-    if (status() == ThreadContext::Unallocated) {
-        cpu->activateWhenReady(tid);
-        return;
-    }
+//    if (status() == ThreadContext::Unallocated) {
+//	cpu->activateWhenReady(tid);
+//	return;
+//   }
 
     _status = ThreadContext::Active;
 
diff --git a/src/cpu/thread_state.cc b/src/cpu/thread_state.cc
index 4b65ca4b8..be8f822f2 100644
--- a/src/cpu/thread_state.cc
+++ b/src/cpu/thread_state.cc
@@ -169,9 +169,8 @@ ThreadState::getMemPort()
         return port;
 
     /* Use this port to for syscall emulation writes to memory. */
-    port = new TranslatingPort(csprintf("%s-%d-funcport",
-                                        baseCpu->name(), tid),
-                               process->pTable, false);
+    port = new TranslatingPort(csprintf("%s-%d-funcport", baseCpu->name(), tid),
+                               process, TranslatingPort::NextPage);
 
     connectToMemFunc(port);