summaryrefslogtreecommitdiff
path: root/src/cpu
diff options
context:
space:
mode:
authorGabe Black <gblack@eecs.umich.edu>2007-05-25 19:29:32 -0700
committerGabe Black <gblack@eecs.umich.edu>2007-05-25 19:29:32 -0700
commita3ae9486d543f23cd4203381e7bcf2ce86c51389 (patch)
treed66d3b9851f3002d0746c7af830062480f83773d /src/cpu
parentad02a59f89139a75dfcfaa7a79498e54f7ce7e5d (diff)
parent44ebb8d3e27329e9f0b501897585359b4ab696f2 (diff)
downloadgem5-a3ae9486d543f23cd4203381e7bcf2ce86c51389.tar.xz
Merge zizzer.eecs.umich.edu:/bk/newmem
into doughnut.mwconnections.com:/home/gblack/m5/newmem-x86 --HG-- extra : convert_revision : 276d00a73b1834d5262129c3f7e0f7fae18e23bc
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/base.cc7
-rw-r--r--src/cpu/memtest/memtest.hh4
-rw-r--r--src/cpu/o3/fetch.hh4
-rw-r--r--src/cpu/o3/lsq.hh4
-rw-r--r--src/cpu/ozone/front_end.hh4
-rw-r--r--src/cpu/ozone/lw_lsq.hh4
-rw-r--r--src/cpu/simple/atomic.hh4
-rw-r--r--src/cpu/simple/timing.cc8
-rw-r--r--src/cpu/simple/timing.hh11
9 files changed, 24 insertions, 26 deletions
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 4dccee0d3..078ae1283 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -179,10 +179,9 @@ BaseCPU::BaseCPU(Params *p)
if (p->functionTraceStart == 0) {
functionTracingEnabled = true;
} else {
- Event *e =
- new EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace>(this,
- true);
- e->schedule(p->functionTraceStart);
+ new EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace>(this,
+ p->functionTraceStart,
+ true);
}
}
#if FULL_SYSTEM
diff --git a/src/cpu/memtest/memtest.hh b/src/cpu/memtest/memtest.hh
index 264309fd7..123ee2a6c 100644
--- a/src/cpu/memtest/memtest.hh
+++ b/src/cpu/memtest/memtest.hh
@@ -115,8 +115,8 @@ class MemTest : public MemObject
virtual void recvRetry();
virtual void getDeviceAddressRanges(AddrRangeList &resp,
- AddrRangeList &snoop)
- { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,0)); }
+ bool &snoop)
+ { resp.clear(); snoop = true; }
};
CpuPort cachePort;
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index 241935416..d9b0a47bd 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -100,8 +100,8 @@ class DefaultFetch
/** Returns the address ranges of this device. */
virtual void getDeviceAddressRanges(AddrRangeList &resp,
- AddrRangeList &snoop)
- { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,0)); }
+ bool &snoop)
+ { resp.clear(); snoop = true; }
/** Timing version of receive. Handles setting fetch to the
* proper status to start fetching. */
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index fd8f878a7..06de608e0 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -316,8 +316,8 @@ class LSQ {
/** Returns the address ranges of this device. */
virtual void getDeviceAddressRanges(AddrRangeList &resp,
- AddrRangeList &snoop)
- { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,0)); }
+ bool &snoop)
+ { resp.clear(); snoop = true; }
/** Timing version of receive. Handles writing back and
* completing the load or store that has returned from
diff --git a/src/cpu/ozone/front_end.hh b/src/cpu/ozone/front_end.hh
index 0acf99ead..667392c06 100644
--- a/src/cpu/ozone/front_end.hh
+++ b/src/cpu/ozone/front_end.hh
@@ -91,8 +91,8 @@ class FrontEnd
/** Returns the address ranges of this device. */
virtual void getDeviceAddressRanges(AddrRangeList &resp,
- AddrRangeList &snoop)
- { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,0)); }
+ bool &snoop)
+ { resp.clear(); snoop = true; }
/** Timing version of receive. Handles setting fetch to the
* proper status to start fetching. */
diff --git a/src/cpu/ozone/lw_lsq.hh b/src/cpu/ozone/lw_lsq.hh
index c981b8e63..2048ad6bb 100644
--- a/src/cpu/ozone/lw_lsq.hh
+++ b/src/cpu/ozone/lw_lsq.hh
@@ -257,8 +257,8 @@ class OzoneLWLSQ {
virtual void recvStatusChange(Status status);
virtual void getDeviceAddressRanges(AddrRangeList &resp,
- AddrRangeList &snoop)
- { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,0)); }
+ bool &snoop)
+ { resp.clear(); snoop = true; }
virtual bool recvTiming(PacketPtr pkt);
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index ad4aa4708..b127e3791 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -104,8 +104,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU
virtual void recvRetry();
virtual void getDeviceAddressRanges(AddrRangeList &resp,
- AddrRangeList &snoop)
- { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,0)); }
+ bool &snoop)
+ { resp.clear(); snoop = true; }
};
CpuPort icachePort;
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index fa7bb4f86..1c79fcf6b 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -168,9 +168,7 @@ TimingSimpleCPU::resume()
delete fetchEvent;
}
- fetchEvent =
- new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false);
- fetchEvent->schedule(nextCycle());
+ fetchEvent = new FetchEvent(this, nextCycle());
}
changeState(SimObject::Running);
@@ -224,9 +222,7 @@ TimingSimpleCPU::activateContext(int thread_num, int delay)
_status = Running;
// kick things off by initiating the fetch of the next instruction
- fetchEvent =
- new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false);
- fetchEvent->schedule(nextCycle(curTick + cycles(delay)));
+ fetchEvent = new FetchEvent(this, nextCycle(curTick + cycles(delay)));
}
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index ef062d24a..39958bfb6 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -66,8 +66,6 @@ class TimingSimpleCPU : public BaseSimpleCPU
Event *drainEvent;
- Event *fetchEvent;
-
private:
class CpuPort : public Port
@@ -93,8 +91,8 @@ class TimingSimpleCPU : public BaseSimpleCPU
virtual void recvStatusChange(Status status);
virtual void getDeviceAddressRanges(AddrRangeList &resp,
- AddrRangeList &snoop)
- { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,0)); }
+ bool &snoop)
+ { resp.clear(); snoop = false; }
struct TickEvent : public Event
{
@@ -199,7 +197,12 @@ class TimingSimpleCPU : public BaseSimpleCPU
void completeIfetch(PacketPtr );
void completeDataAccess(PacketPtr );
void advanceInst(Fault fault);
+
private:
+
+ typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;
+ FetchEvent *fetchEvent;
+
void completeDrain();
};