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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-04-04 11:42:28 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-04-04 11:42:28 -0500 |
| commit | a679cd917ac4775979e23594de52f1bca407c08c (patch) | |
| tree | d48bb74b729d2e11e62e1db9a4fb860b70ddd1b3 /src/cpu | |
| parent | ac650199eeb62bf05fec11a4f2d7666cbd31331c (diff) | |
| download | gem5-a679cd917ac4775979e23594de52f1bca407c08c.tar.xz | |
ARM: Cleanup implementation of ITSTATE and put important code in PCState.
Consolidate all code to handle ITSTATE in the PCState object rather than
touching a variety of structures/objects.
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/o3/fetch_impl.hh | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 6c1ac456d..c611f0e49 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -821,8 +821,6 @@ DefaultFetch<Impl>::squash(const TheISA::PCState &newPC, DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n", tid); doSquash(newPC, tid); - if (squashInst) - predecoder.reset(squashInst->staticInst->machInst); // Tell the CPU to remove any instructions that are not in the ROB. cpu->removeInstsNotInROB(tid); |