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authorAndreas Hansson <andreas.hansson@arm.com>2015-03-02 04:00:42 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2015-03-02 04:00:42 -0500
commitd64b34bef82e6ea8a2438d92224d8d093df47d59 (patch)
tree508d527a16f07d9f3d456143a594c01667a20b8d /src/cpu
parentbd70db552112570e41838748f0d2a5168acd974a (diff)
downloadgem5-d64b34bef82e6ea8a2438d92224d8d093df47d59.tar.xz
arm: Share a port for the two table walker objects
This patch changes how the MMU and table walkers are created such that a single port is used to connect the MMU and the TLBs to the memory system. Previously two ports were needed as there are two table walker objects (stage one and stage two), and they both had a port. Now the port itself is moved to the Stage2MMU, and each TableWalker is simply using the port from the parent. By using the same port we also remove the need for having an additional crossbar joining the two ports before the walker cache or the L2. This simplifies the creation of the CPU cache topology in BaseCPU.py considerably. Moreover, for naming and symmetry reasons, the TLB walker port is connected through the stage-one table walker thus making the naming identical to x86. Along the same line, we use the stage-one table walker to generate the master id that is used by all TLB-related requests.
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/BaseCPU.py26
1 files changed, 3 insertions, 23 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 052df5702..ee6c05f46 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012-2013 ARM Limited
+# Copyright (c) 2012-2013, 2015 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -214,9 +214,6 @@ class BaseCPU(MemObject):
if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
_cached_ports += ["itb.walker.port", "dtb.walker.port"]
- if buildEnv['TARGET_ISA'] in ['arm']:
- _cached_ports += ["istage2_mmu.stage2_tlb.walker.port",
- "dstage2_mmu.stage2_tlb.walker.port"]
_uncached_slave_ports = []
_uncached_master_ports = []
@@ -273,35 +270,18 @@ class BaseCPU(MemObject):
if iwc and dwc:
self.itb_walker_cache = iwc
self.dtb_walker_cache = dwc
- if buildEnv['TARGET_ISA'] in ['arm']:
- self.itb_walker_cache_bus = CoherentXBar()
- self.dtb_walker_cache_bus = CoherentXBar()
- self.itb_walker_cache_bus.master = iwc.cpu_side
- self.dtb_walker_cache_bus.master = dwc.cpu_side
- self.itb.walker.port = self.itb_walker_cache_bus.slave
- self.dtb.walker.port = self.dtb_walker_cache_bus.slave
- self.istage2_mmu.stage2_tlb.walker.port = self.itb_walker_cache_bus.slave
- self.dstage2_mmu.stage2_tlb.walker.port = self.dtb_walker_cache_bus.slave
- else:
- self.itb.walker.port = iwc.cpu_side
- self.dtb.walker.port = dwc.cpu_side
+ self.itb.walker.port = iwc.cpu_side
+ self.dtb.walker.port = dwc.cpu_side
self._cached_ports += ["itb_walker_cache.mem_side", \
"dtb_walker_cache.mem_side"]
else:
self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
- if buildEnv['TARGET_ISA'] in ['arm']:
- self._cached_ports += ["istage2_mmu.stage2_tlb.walker.port", \
- "dstage2_mmu.stage2_tlb.walker.port"]
-
# Checker doesn't need its own tlb caches because it does
# functional accesses only
if self.checker != NULL:
self._cached_ports += ["checker.itb.walker.port", \
"checker.dtb.walker.port"]
- if buildEnv['TARGET_ISA'] in ['arm']:
- self._cached_ports += ["checker.istage2_mmu.stage2_tlb.walker.port", \
- "checker.dstage2_mmu.stage2_tlb.walker.port"]
def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)