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authorGabe Black <gblack@eecs.umich.edu>2007-11-12 14:38:31 -0800
committerGabe Black <gblack@eecs.umich.edu>2007-11-12 14:38:31 -0800
commitfce45baf178b43c2ea1476967fba3766e9b2ea9d (patch)
tree1aa3ba357950f9a18e2d7a7e6fd4be8c8d0e5d91 /src/cpu
parentf17f3d20be08d25f176138691a29897df54e5cc0 (diff)
downloadgem5-fce45baf178b43c2ea1476967fba3766e9b2ea9d.tar.xz
X86: Work on the page table walker, TLB, and related faults.
--HG-- extra : convert_revision : 9edde958b7e571c07072785f18f9109f73b8059f
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/BaseCPU.py4
-rw-r--r--src/cpu/simple/base.cc2
2 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 1af30a532..cb5793e57 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -100,7 +100,7 @@ class BaseCPU(SimObject):
_mem_ports = []
- if build_env['TARGET_ISA'] == 'x86':
+ if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']:
itb.walker_port = Port("ITB page table walker port")
dtb.walker_port = Port("ITB page table walker port")
_mem_ports = ["itb.walker_port", "dtb.walker_port"]
@@ -117,7 +117,7 @@ class BaseCPU(SimObject):
self.icache_port = ic.cpu_side
self.dcache_port = dc.cpu_side
self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
- if build_env['TARGET_ISA'] == 'x86':
+ if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']:
self._mem_ports += ["itb.walker_port", "dtb.walker_port"]
def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 1611a7275..98e29d8d1 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -466,9 +466,9 @@ BaseSimpleCPU::advancePC(Fault fault)
if (fault != NoFault) {
curMacroStaticInst = StaticInst::nullStaticInstPtr;
predecoder.reset();
- fault->invoke(tc);
thread->setMicroPC(0);
thread->setNextMicroPC(1);
+ fault->invoke(tc);
} else {
//If we're at the last micro op for this instruction
if (curStaticInst && curStaticInst->isLastMicroop()) {