base: add support for probe points and common probes

The probe patch is motivated by the desire to move analytical and trace code
away from functional code. This is achieved by the probe interface which is
essentially a glorified observer model.

What this means to users:
* add a probe point and a "notify" call at the source of an "event"
* add an isolated module, that is being used to carry out *your* analysis (e.g. generate a trace)
* register that module as a probe listener
Note: an example is given for reference in src/cpu/o3/simple_trace.[hh|cc] and src/cpu/SimpleTrace.py

What is happening under the hood:
* every SimObject maintains has a ProbeManager.
* during initialization (src/python/m5/simulate.py) first regProbePoints and
  the regProbeListeners is called on each SimObject.  this hooks up the probe
  point notify calls with the listeners.

FAQs:
Why did you develop probe points:
* to remove trace, stats gathering, analytical code out of the functional code.
* the belief that probes could be generically useful.

What is a probe point:
* a probe point is used to notify upon a given event (e.g. cpu commits an instruction)

What is a probe listener:
* a class that handles whatever the user wishes to do when they are notified
  about an event.

What can be passed on notify:
* probe points are templates, and so the user can generate probes that pass any
  type of argument (by const reference) to a listener.

What relationships can be generated (1:1, 1:N, N:M etc):
* there isn't a restriction. You can hook probe points and listeners up in a
  1:1, 1:N, N:M relationship. They become useful when a number of modules
  listen to the same probe points. The idea being that you can add a small
  number of probes into the source code and develop a larger number of useful
  analysis modules that use information passed by the probes.

Can you give examples:
* adding a probe point to the cpu's commit method allows you to build a trace
  module (outputting assembler), you could re-use this to gather instruction
  distribution (arithmetic, load/store, conditional, control flow) stats.

Why is the probe interface currently restricted to passing a const reference:
* the desire, initially at least, is to allow an interface to observe
  functionality, but not to change functionality.
* of course this can be subverted by const-casting.

What is the performance impact of adding probes:
* when nothing is actively listening to the probes they should have a
  relatively minor impact. Profiling has suggested even with a large number of
  probes (60) the impact of them (when not active) is very minimal (<1%).

13 files changed, 302 insertions, 1 deletions

diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index 62aa274c2..cd663e2df 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -50,6 +50,7 @@
 #include "cpu/exetrace.hh"
 #include "cpu/inst_seq.hh"
 #include "cpu/timebuf.hh"
+#include "sim/probe/probe.hh"
 
 struct DerivO3CPUParams;
 
@@ -150,6 +151,10 @@ class DefaultCommit
     /** Commit policy used in SMT mode. */
     CommitPolicy commitPolicy;
 
+    /** Probe Points. */
+    ProbePointArg<DynInstPtr> *ppCommit;
+    ProbePointArg<DynInstPtr> *ppCommitStall;
+
   public:
     /** Construct a DefaultCommit with the given parameters. */
     DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params);
@@ -160,6 +165,9 @@ class DefaultCommit
     /** Registers statistics. */
     void regStats();
 
+    /** Registers probes. */
+    void regProbePoints();
+
     /** Sets the list of threads. */
     void setThreads(std::vector<Thread *> &threads);
 
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 6664faf95..a6f2a63db 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -163,6 +163,14 @@ DefaultCommit<Impl>::name() const
 
 template <class Impl>
 void
+DefaultCommit<Impl>::regProbePoints()
+{
+    ppCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Commit");
+    ppCommitStall = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "CommitStall");
+}
+
+template <class Impl>
+void
 DefaultCommit<Impl>::regStats()
 {
     using namespace Stats;
@@ -705,6 +713,8 @@ DefaultCommit<Impl>::tick()
         } else if (!rob->isEmpty(tid)) {
             DynInstPtr inst = rob->readHeadInst(tid);
 
+            ppCommitStall->notify(inst);
+
             DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
                     "%s is head of ROB and not ready\n",
                     tid, inst->seqNum, inst->pcState());
@@ -1017,6 +1027,7 @@ DefaultCommit<Impl>::commitInsts()
 
             if (commit_success) {
                 ++num_committed;
+                ppCommit->notify(head_inst);
 
                 changedROBNumEntries[tid] = true;
 
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 515d87f1b..710482d3c 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -468,6 +468,17 @@ FullO3CPU<Impl>::~FullO3CPU()
 
 template <class Impl>
 void
+FullO3CPU<Impl>::regProbePoints()
+{
+    ppInstAccessComplete = new ProbePointArg<PacketPtr>(getProbeManager(), "InstAccessComplete");
+    ppDataAccessComplete = new ProbePointArg<std::pair<DynInstPtr, PacketPtr> >(getProbeManager(), "DataAccessComplete");
+    fetch.regProbePoints();
+    iew.regProbePoints();
+    commit.regProbePoints();
+}
+
+template <class Impl>
+void
 FullO3CPU<Impl>::regStats()
 {
     BaseO3CPU::regStats();
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 18b75948f..dadee5d56 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -375,6 +375,12 @@ class FullO3CPU : public BaseO3CPU
     /** Registers statistics. */
     void regStats();
 
+    ProbePointArg<PacketPtr> *ppInstAccessComplete;
+    ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete;
+
+    /** Register probe points. */
+    void regProbePoints();
+
     void demapPage(Addr vaddr, uint64_t asn)
     {
         this->itb->demapPage(vaddr, asn);
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index 6ef604af3..eba4469c0 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -55,6 +55,7 @@
 #include "mem/packet.hh"
 #include "mem/port.hh"
 #include "sim/eventq.hh"
+#include "sim/probe/probe.hh"
 
 struct DerivO3CPUParams;
 
@@ -194,6 +195,9 @@ class DefaultFetch
     /** List that has the threads organized by priority. */
     std::list<ThreadID> priorityList;
 
+    /** Probe points. */
+    ProbePointArg<DynInstPtr> *ppFetch;
+
   public:
     /** DefaultFetch constructor. */
     DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params);
@@ -204,6 +208,9 @@ class DefaultFetch
     /** Registers statistics. */
     void regStats();
 
+    /** Registers probes. */
+    void regProbePoints();
+
     /** Sets the main backwards communication time buffer pointer. */
     void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
 
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index b121ba707..5b04c2a25 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -163,6 +163,13 @@ DefaultFetch<Impl>::name() const
 
 template <class Impl>
 void
+DefaultFetch<Impl>::regProbePoints()
+{
+    ppFetch = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Fetch");
+}
+
+template <class Impl>
+void
 DefaultFetch<Impl>::regStats()
 {
     icacheStallCycles
@@ -401,6 +408,7 @@ DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
     }
 
     pkt->req->setAccessLatency();
+    cpu->ppInstAccessComplete->notify(pkt);
     // Reset the mem req to NULL.
     delete pkt->req;
     delete pkt;
@@ -666,7 +674,6 @@ DefaultFetch<Impl>::finishTranslation(Fault fault, RequestPtr mem_req)
             DPRINTF(Fetch, "[tid:%i]: Doing Icache access.\n", tid);
             DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
                     "response.\n", tid);
-
             lastIcacheStall[tid] = curTick();
             fetchStatus[tid] = IcacheWaitResponse;
         }
@@ -1312,6 +1319,7 @@ DefaultFetch<Impl>::fetch(bool &status_change)
                 buildInst(tid, staticInst, curMacroop,
                           thisPC, nextPC, true);
 
+            ppFetch->notify(instruction);
             numInst++;
 
 #if TRACING_ON
diff --git a/src/cpu/o3/iew.hh b/src/cpu/o3/iew.hh
index 1213cf12b..24412e11f 100644
--- a/src/cpu/o3/iew.hh
+++ b/src/cpu/o3/iew.hh
@@ -52,6 +52,7 @@
 #include "cpu/o3/scoreboard.hh"
 #include "cpu/timebuf.hh"
 #include "debug/IEW.hh"
+#include "sim/probe/probe.hh"
 
 struct DerivO3CPUParams;
 class FUPool;
@@ -122,6 +123,10 @@ class DefaultIEW
     /** Writeback status. */
     StageStatus wbStatus;
 
+    /** Probe points. */
+    ProbePointArg<DynInstPtr> *ppMispredict;
+    ProbePointArg<DynInstPtr> *ppDispatch;
+
   public:
     /** Constructs a DefaultIEW with the given parameters. */
     DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params);
@@ -132,6 +137,9 @@ class DefaultIEW
     /** Registers statistics. */
     void regStats();
 
+    /** Registers probes. */
+    void regProbePoints();
+
     /** Initializes stage; sends back the number of free IQ and LSQ entries. */
     void startupStage();
 
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index 6c5c57fb7..9cfbb3cfc 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -113,6 +113,14 @@ DefaultIEW<Impl>::name() const
 
 template <class Impl>
 void
+DefaultIEW<Impl>::regProbePoints()
+{
+    ppDispatch = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Dispatch");
+    ppMispredict = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Mispredict");
+}
+
+template <class Impl>
+void
 DefaultIEW<Impl>::regStats()
 {
     using namespace Stats;
@@ -1158,6 +1166,7 @@ DefaultIEW<Impl>::dispatchInsts(ThreadID tid)
 #if TRACING_ON
         inst->dispatchTick = curTick() - inst->fetchTick;
 #endif
+        ppDispatch->notify(inst);
     }
 
     if (!insts_to_dispatch.empty()) {
@@ -1357,6 +1366,8 @@ DefaultIEW<Impl>::executeInsts()
                 // If incorrect, then signal the ROB that it must be squashed.
                 squashDueToBranch(inst, tid);
 
+                ppMispredict->notify(inst);
+
                 if (inst->readPredTaken()) {
                     predictedTakenIncorrect++;
                 } else {
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index ade076995..277fe48d2 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -131,6 +131,8 @@ LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
     }
 
     pkt->req->setAccessLatency();
+    cpu->ppDataAccessComplete->notify(std::make_pair(inst, pkt));
+
     delete state;
     delete pkt->req;
     delete pkt;
diff --git a/src/cpu/o3/probe/SConscript b/src/cpu/o3/probe/SConscript
new file mode 100644
index 000000000..c8ab2b53f
--- /dev/null
+++ b/src/cpu/o3/probe/SConscript
@@ -0,0 +1,45 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2013 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Matt Horsnell
+
+Import('*')
+
+if 'O3CPU' in env['CPU_MODELS']:
+    SimObject('SimpleTrace.py')
+    Source('simple_trace.cc')
+    DebugFlag('SimpleTrace')
diff --git a/src/cpu/o3/probe/SimpleTrace.py b/src/cpu/o3/probe/SimpleTrace.py
new file mode 100644
index 000000000..eeec58ef0
--- /dev/null
+++ b/src/cpu/o3/probe/SimpleTrace.py
@@ -0,0 +1,42 @@
+# Copyright (c) 2013 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Matt Horsnell
+
+from Probe import *
+
+class SimpleTrace(ProbeListenerObject):
+    type = 'SimpleTrace'
+    cxx_header = 'cpu/o3/probe/simple_trace.hh'
diff --git a/src/cpu/o3/probe/simple_trace.cc b/src/cpu/o3/probe/simple_trace.cc
new file mode 100644
index 000000000..35d1365cb
--- /dev/null
+++ b/src/cpu/o3/probe/simple_trace.cc
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2013 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Matt Horsnell
+ */
+
+#include "base/trace.hh"
+#include "cpu/o3/probe/simple_trace.hh"
+#include "debug/SimpleTrace.hh"
+
+void SimpleTrace::traceCommit(const O3CPUImpl::DynInstPtr &dynInst)
+{
+    DPRINTFR(SimpleTrace, "[%s]: Commit 0x%08x %s.\n", name(),
+             dynInst->instAddr(),
+             dynInst->staticInst->disassemble(dynInst->instAddr()));
+}
+
+void SimpleTrace::traceFetch(const O3CPUImpl::DynInstPtr &dynInst)
+{
+    DPRINTFR(SimpleTrace, "[%s]: Fetch 0x%08x %s.\n", name(),
+             dynInst->instAddr(),
+             dynInst->staticInst->disassemble(dynInst->instAddr()));
+}
+
+void SimpleTrace::regProbeListeners()
+{
+    typedef ProbeListenerArg<SimpleTrace, O3CPUImpl::DynInstPtr> DynInstListener;
+    listeners.push_back(new DynInstListener(this, "Commit", &SimpleTrace::traceCommit));
+    listeners.push_back(new DynInstListener(this, "Fetch", &SimpleTrace::traceFetch));
+}
+
+SimpleTrace*
+SimpleTraceParams::create()
+{
+    return new SimpleTrace(this);
+}
diff --git a/src/cpu/o3/probe/simple_trace.hh b/src/cpu/o3/probe/simple_trace.hh
new file mode 100644
index 000000000..663128810
--- /dev/null
+++ b/src/cpu/o3/probe/simple_trace.hh
@@ -0,0 +1,73 @@
+ /*
+ * Copyright (c) 2013 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Matt Horsnell
+ */
+
+/**
+ * @file This file initializes a simple trace unit which listens to
+ * a probe point in the fetch and commit stage of the O3 pipeline
+ * and simply outputs those events as a dissassembled instruction stream
+ * to the trace output.
+ */
+#ifndef __CPU_O3_PROBE_SIMPLE_TRACE_HH__
+#define __CPU_O3_PROBE_SIMPLE_TRACE_HH__
+
+#include "cpu/o3/dyn_inst.hh"
+#include "cpu/o3/impl.hh"
+#include "params/SimpleTrace.hh"
+#include "sim/probe/probe.hh"
+
+class SimpleTrace : public ProbeListenerObject {
+
+  public:
+    SimpleTrace(const SimpleTraceParams *params):
+        ProbeListenerObject(params)
+    {
+    }
+
+    /** Register the probe listeners. */
+    void regProbeListeners();
+
+    /** Returns the name of the trace. */
+    const std::string name() const { return ProbeListenerObject::name() + ".trace"; }
+
+  private:
+    void traceFetch(const O3CPUImpl::DynInstPtr &dynInst);
+    void traceCommit(const O3CPUImpl::DynInstPtr &dynInst);
+
+};
+#endif//__CPU_O3_PROBE_SIMPLE_TRACE_HH__