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| author | Timothy M. Jones <tjones1@inf.ed.ac.uk> | 2009-10-27 09:24:39 -0700 |
|---|---|---|
| committer | Timothy M. Jones <tjones1@inf.ed.ac.uk> | 2009-10-27 09:24:39 -0700 |
| commit | 835a55e7f347697815fc43851b2dd5a8642d21c4 (patch) | |
| tree | 637768b1de6de2bc4520fad97f90194ad6d3f8d6 /src/cpu | |
| parent | 0fdfc82bde5b8975ee93d5da9c604ad9b99942e0 (diff) | |
| download | gem5-835a55e7f347697815fc43851b2dd5a8642d21c4.tar.xz | |
POWER: Add support for the Power ISA
This adds support for the 32-bit, big endian Power ISA. This supports both
integer and floating point instructions based on the Power ISA Book I v2.06.
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/BaseCPU.py | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 75114053e..ac734e5ac 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -59,6 +59,10 @@ elif buildEnv['TARGET_ISA'] == 'arm': from ArmTLB import ArmTLB if buildEnv['FULL_SYSTEM']: from ArmInterrupts import ArmInterrupts +elif buildEnv['TARGET_ISA'] == 'power': + from PowerTLB import PowerTLB + if buildEnv['FULL_SYSTEM']: + from PowerInterrupts import PowerInterrupts class BaseCPU(MemObject): type = 'BaseCPU' @@ -116,6 +120,13 @@ class BaseCPU(MemObject): if buildEnv['FULL_SYSTEM']: interrupts = Param.ArmInterrupts( ArmInterrupts(), "Interrupt Controller") + elif buildEnv['TARGET_ISA'] == 'power': + UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") + dtb = Param.PowerTLB(PowerTLB(), "Data TLB") + itb = Param.PowerTLB(PowerTLB(), "Instruction TLB") + if buildEnv['FULL_SYSTEM']: + interrupts = Param.PowerInterrupts( + PowerInterrupts(), "Interrupt Controller") else: print "Don't know what TLB to use for ISA %s" % \ buildEnv['TARGET_ISA'] |