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author | Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> | 2011-02-11 18:29:35 -0600 |
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committer | Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> | 2011-02-11 18:29:35 -0600 |
commit | a05032f4df8be28c0ceaefba03114f3e7a5f6ab4 (patch) | |
tree | 300a7d3ae0a072f5c44310d20a1fc1b5581ca02d /src/cpu | |
parent | 74eff1b71b7f2075e72a06e611d07ea37638e0b6 (diff) | |
download | gem5-a05032f4df8be28c0ceaefba03114f3e7a5f6ab4.tar.xz |
O3: Fix pipeline restart when a table walk completes in the fetch stage.
When a table walk is initiated by the fetch stage, the CPU can
potentially move to the idle state and never wake up.
The fetch stage must call cpu->wakeCPU() when a translation completes
(in finishTranslation()).
Diffstat (limited to 'src/cpu')
-rw-r--r-- | src/cpu/o3/fetch_impl.hh | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index d0c83d586..2e4e4819e 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -604,6 +604,9 @@ DefaultFetch<Impl>::finishTranslation(Fault fault, RequestPtr mem_req) ThreadID tid = mem_req->threadId(); Addr block_PC = mem_req->getVaddr(); + // Wake up CPU if it was idle + cpu->wakeCPU(); + // If translation was successful, attempt to read the icache block. if (fault == NoFault) { // Build packet here. @@ -654,6 +657,9 @@ DefaultFetch<Impl>::finishTranslation(Fault fault, RequestPtr mem_req) instruction->fault = fault; wroteToTimeBuffer = true; + DPRINTF(Activity, "Activity this cycle.\n"); + cpu->activityThisCycle(); + fetchStatus[tid] = TrapPending; DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n", tid); |