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authorAli Saidi <saidi@eecs.umich.edu>2006-11-09 18:22:46 -0500
committerAli Saidi <saidi@eecs.umich.edu>2006-11-09 18:22:46 -0500
commitcb172d0332ecf4ff7f6329f1172d8e1cf78767e2 (patch)
tree1ccfc27346a63acf9510f43c7590204c6bb72ab9 /src/cpu
parentf4aa4e43c41fa688abbee9dfa5b2a35a44b2dcf5 (diff)
downloadgem5-cb172d0332ecf4ff7f6329f1172d8e1cf78767e2.tar.xz
Get SPARC to the point that it starts running. Add ability to load the ROM bin files, cleanup lockstep printing a bit
Since we don't have a platform yet, you need to comment out the default responder stuff in Bus.py to make it work. SConstruct: Add TARGET_ISA to the list of environment variables that end up in the build_env for python configs/common/FSConfig.py: add a simple SPARC system to being testing with, you'll need to change makeLinuxAlphaSystem to makeSparcSystem in fs.py for now src/SConscript: add a raw file object, at least until we get more info about how to compile openboot properly src/arch/sparc/system.cc: src/arch/sparc/system.hh: add parameters for ROM files (OBP/Reset/Hypervisor), a ROM, load files into ROM src/base/loader/object_file.cc: src/base/loader/object_file.hh: add option to try raw when nothing works src/cpu/exetrace.cc: cleanup lockstep printing a little bit src/cpu/m5legion_interface.h: change the instruction to be 32 bits because it is src/mem/physical.cc: fix assert that doesn't work if memory starts somewhere above 0 src/python/m5/objects/BaseCPU.py: Add if statement to choose between sparc tlbs and alpha tlbs src/python/m5/objects/System.py: Add a sparc system that sets the rom addresses correctly src/python/m5/params.py: add the ability to add Addr() together --HG-- extra : convert_revision : bbbd8a56134f2dda2728091f740e2f7119b0c4af
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/exetrace.cc111
-rw-r--r--src/cpu/m5legion_interface.h4
2 files changed, 68 insertions, 47 deletions
diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index 80b144e85..881fbbd9b 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -37,6 +37,7 @@
#include <sys/shm.h>
#include "arch/regfile.hh"
+#include "arch/utility.hh"
#include "base/loader/symtab.hh"
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
@@ -231,6 +232,7 @@ Trace::InstRecord::dump(ostream &outs)
//
outs << endl;
}
+#if THE_ISA == SPARC_ISA
// Compare
if (flags[LEGION_LOCKSTEP])
{
@@ -239,57 +241,76 @@ Trace::InstRecord::dump(ostream &outs)
bool diffInst = false;
bool diffRegs = false;
- while (!compared) {
- if (shared_data->flags == OWN_M5) {
- if (shared_data->pc != PC)
- diffPC = true;
- if (shared_data->instruction != staticInst->machInst)
- diffInst = true;
- for (int i = 0; i < TheISA::NumIntRegs; i++) {
- if (thread->readIntReg(i) != shared_data->intregs[i])
- diffRegs = true;
- }
-
- if (diffPC || diffInst || diffRegs ) {
- outs << "Differences found between M5 and Legion:";
- if (diffPC)
- outs << " PC";
- if (diffInst)
- outs << " Instruction";
- if (diffRegs)
- outs << " IntRegs";
- outs << endl;
-
- outs << "M5 PC: " << setw(20) << "0x" << hex << PC;
- outs << "Legion PC: " << setw(20) << "0x" << hex <<
- shared_data->pc << endl;
-
-
-
- outs << "M5 Instruction: " << staticInst->machInst << "("
- << staticInst->disassemble(PC, debugSymbolTable)
- << ")" << "Legion Instruction: " <<
- shared_data->instruction << "("
- /*<< legionInst->disassemble(shared_data->pc,
- debugSymbolTable)*/
- << ")" << endl;
-
+ if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) {
+ while (!compared) {
+ if (shared_data->flags == OWN_M5) {
+ if (shared_data->pc != PC)
+ diffPC = true;
+ if (shared_data->instruction != staticInst->machInst)
+ diffInst = true;
for (int i = 0; i < TheISA::NumIntRegs; i++) {
- outs << setw(16) << "0x" << hex << thread->readIntReg(i)
- << setw(16) << "0x" << hex << shared_data->intregs[i];
-
if (thread->readIntReg(i) != shared_data->intregs[i])
- outs << "<--- Different";
- outs << endl;
+ diffRegs = true;
}
- }
- compared = true;
- shared_data->flags = OWN_LEGION;
- }
- }
+ if (diffPC || diffInst || diffRegs ) {
+ outs << "Differences found between M5 and Legion:";
+ if (diffPC)
+ outs << " [PC]";
+ if (diffInst)
+ outs << " [Instruction]";
+ if (diffRegs)
+ outs << " [IntRegs]";
+ outs << endl << endl;;
+
+ outs << setfill(' ') << setw(15)
+ << "M5 PC: " << "0x"<< setw(16) << setfill('0')
+ << hex << PC << endl;
+ outs << setfill(' ') << setw(15)
+ << "Legion PC: " << "0x"<< setw(16) << setfill('0') << hex
+ << shared_data->pc << endl << endl;
+
+ outs << setfill(' ') << setw(15)
+ << "M5 Inst: " << "0x"<< setw(8)
+ << setfill('0') << hex << staticInst->machInst
+ << staticInst->disassemble(PC, debugSymbolTable)
+ << endl;
+
+ StaticInstPtr legionInst = StaticInst::decode(makeExtMI(shared_data->instruction, thread));
+ outs << setfill(' ') << setw(15)
+ << " Legion Inst: "
+ << "0x" << setw(8) << setfill('0') << hex
+ << shared_data->instruction
+ << legionInst->disassemble(shared_data->pc, debugSymbolTable)
+ << endl;
+
+ outs << endl;
+ static const char * regtypes[4] = {"%g", "%o", "%l", "%i"};
+ for(int y = 0; y < 4; y++)
+ {
+ for(int x = 0; x < 8; x++)
+ {
+ outs << regtypes[y] << x << " " ;
+ outs << "0x" << hex << setw(16) << thread->readIntReg(y*8+x);
+ if (thread->readIntReg(y*8 + x) != shared_data->intregs[y*8+x])
+ outs << " X ";
+ else
+ outs << " | ";
+ outs << "0x" << setw(16) << hex << shared_data->intregs[y*8+x]
+ << endl;
+ }
+ }
+ fatal("Differences found between Legion and M5\n");
+ }
+
+ compared = true;
+ shared_data->flags = OWN_LEGION;
+ }
+ } // while
+ } // if not microop
}
+#endif
}
diff --git a/src/cpu/m5legion_interface.h b/src/cpu/m5legion_interface.h
index 0fa0e7279..9338d9ca0 100644
--- a/src/cpu/m5legion_interface.h
+++ b/src/cpu/m5legion_interface.h
@@ -30,7 +30,7 @@
#include <unistd.h>
-#define VERSION 0xA1000001
+#define VERSION 0xA1000002
#define OWN_M5 0x000000AA
#define OWN_LEGION 0x00000055
@@ -41,7 +41,7 @@ typedef struct {
uint32_t version;
uint64_t pc;
- uint64_t instruction;
+ uint32_t instruction;
uint64_t intregs[32];
} SharedData;