scons: Switch from the print statement to the print function.

Starting with version 3, scons imposes using the print function instead
of the print statement in code it processes. To get things building
again, this change moves all python code within gem5 to use the
function version. Another change by another author separately made this
same change to the site_tools and site_init.py files.

Change-Id: I2de7dc3b1be756baad6f60574c47c8b7e80ea3b0
Reviewed-on: https://gem5-review.googlesource.com/8761
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

4 files changed, 15 insertions, 7 deletions

diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 096aa635e..e02d36724 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -42,6 +42,8 @@
 #          Andreas Hansson
 #          Glenn Bergmans
 
+from __future__ import print_function
+
 import sys
 
 from m5.SimObject import *
@@ -200,8 +202,8 @@ class BaseCPU(MemObject):
                 [], "Interrupt Controller")
         isa = VectorParam.RiscvISA([], "ISA instance")
     else:
-        print "Don't know what TLB to use for ISA %s" % \
-            buildEnv['TARGET_ISA']
+        print("Don't know what TLB to use for ISA %s" %
+              buildEnv['TARGET_ISA'])
         sys.exit(1)
 
     max_insts_all_threads = Param.Counter(0,
@@ -260,8 +262,8 @@ class BaseCPU(MemObject):
             self.interrupts = \
                 [RiscvInterrupts() for i in xrange(self.numThreads)]
         else:
-            print "Don't know what Interrupt Controller to use for ISA %s" % \
-                buildEnv['TARGET_ISA']
+            print("Don't know what Interrupt Controller to use for ISA %s" %
+                  buildEnv['TARGET_ISA'])
             sys.exit(1)
 
     def connectCachedPorts(self, bus):
diff --git a/src/cpu/minor/MinorCPU.py b/src/cpu/minor/MinorCPU.py
index 5954f7b1e..87a30497c 100644
--- a/src/cpu/minor/MinorCPU.py
+++ b/src/cpu/minor/MinorCPU.py
@@ -40,6 +40,8 @@
 #          Nathan Binkert
 #          Andrew Bardsley
 
+from __future__ import print_function
+
 from m5.defines import buildEnv
 from m5.params import *
 from m5.proxy import *
@@ -275,5 +277,5 @@ class MinorCPU(BaseCPU):
         numThreads = Parent.numThreads), "Branch Predictor")
 
     def addCheckerCpu(self):
-        print "Checker not yet supported by MinorCPU"
+        print("Checker not yet supported by MinorCPU")
         exit(1)
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py
index 8507ab6ff..b8152f663 100644
--- a/src/cpu/o3/O3CPU.py
+++ b/src/cpu/o3/O3CPU.py
@@ -38,6 +38,8 @@
 #
 # Authors: Kevin Lim
 
+from __future__ import print_function
+
 from m5.defines import buildEnv
 from m5.params import *
 from m5.proxy import *
@@ -173,5 +175,5 @@ class DerivO3CPU(BaseCPU):
             self.checker.cpu_id = self.cpu_id
 
         else:
-            print "ERROR: Checker only supported under ARM ISA!"
+            print("ERROR: Checker only supported under ARM ISA!")
             exit(1)
diff --git a/src/cpu/simple/BaseSimpleCPU.py b/src/cpu/simple/BaseSimpleCPU.py
index 7298724ea..b40458482 100644
--- a/src/cpu/simple/BaseSimpleCPU.py
+++ b/src/cpu/simple/BaseSimpleCPU.py
@@ -26,6 +26,8 @@
 #
 # Authors: Gabe Black
 
+from __future__ import print_function
+
 from m5.defines import buildEnv
 from m5.params import *
 from BaseCPU import BaseCPU
@@ -45,7 +47,7 @@ class BaseSimpleCPU(BaseCPU):
             self.checker.itb = ArmTLB(size = self.itb.size)
             self.checker.dtb = ArmTLB(size = self.dtb.size)
         else:
-            print "ERROR: Checker only supported under ARM ISA!"
+            print("ERROR: Checker only supported under ARM ISA!")
             exit(1)
 
     branchPred = Param.BranchPredictor(NULL, "Branch Predictor")