Add base ARM code to M5

--HG--
extra : convert_revision : d811bf87d1a0bfc712942ecd3db1b48fc75257af

4 files changed, 23 insertions, 5 deletions

diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index ee5ed0774..c2a865113 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2005-2007 The Regents of The University of Michigan
+# Copyright (c) 2005-2008 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -45,6 +45,8 @@ elif build_env['TARGET_ISA'] == 'x86':
     from X86TLB import X86DTB, X86ITB
 elif build_env['TARGET_ISA'] == 'mips':
     from MipsTLB import MipsTLB,MipsDTB, MipsITB, MipsUTB
+elif build_env['TARGET_ISA'] == 'arm':
+    from ArmTLB import ArmTLB, ArmDTB, ArmITB, ArmUTB
 
 class BaseCPU(SimObject):
     type = 'BaseCPU'
@@ -76,6 +78,11 @@ class BaseCPU(SimObject):
         dtb = Param.MipsDTB(MipsDTB(), "Data TLB")
         itb = Param.MipsITB(MipsITB(), "Instruction TLB")
         tlb = Param.MipsUTB(MipsUTB(), "Unified TLB")
+    elif build_env['TARGET_ISA'] == 'arm':
+        UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
+        dtb = Param.ArmDTB(ArmDTB(), "Data TLB")
+        itb = Param.ArmITB(ArmITB(), "Instruction TLB")
+        tlb = Param.ArmUTB(ArmUTB(), "Unified TLB")
     else:
         print "Don't know what TLB to use for ISA %s" % \
             build_env['TARGET_ISA']
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index c37f8007e..a1f9e0591 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -49,6 +49,10 @@
     template <class Impl> class X86DynInst;
     struct X86SimpleImpl;
     typedef X86DynInst<X86SimpleImpl> O3DynInst;
+#elif THE_ISA == ARM_ISA
+    template <class Impl> class ArmDynInst;
+    struct ArmSimpleImpl;
+    typedef ArmDynInst<ArmSimpleImpl> O3DynInst;
 #else
     #error "O3DynInst not defined for this ISA"
 #endif
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index fc35f2666..e1fc6882f 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -598,13 +598,19 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
             assert(fault == NoFault);
         } else {
             if (fault == NoFault) {
+                // Note that ARM can have NULL packets if the instruction gets
+                // squashed due to predication
                 // early fail on store conditional: complete now
-                assert(dcache_pkt != NULL);
+                assert(dcache_pkt != NULL || THE_ISA == ARM_ISA);
+
                 fault = curStaticInst->completeAcc(dcache_pkt, this,
                                                    traceData);
-                delete dcache_pkt->req;
-                delete dcache_pkt;
-                dcache_pkt = NULL;
+                if (dcache_pkt != NULL)
+                {
+                    delete dcache_pkt->req;
+                    delete dcache_pkt;
+                    dcache_pkt = NULL;
+                }
 
                 // keep an instruction count
                 if (fault == NoFault)
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index d2232bab7..ceda78d90 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -259,6 +259,7 @@ class StaticInstBase : public RefCounted
     bool isMicroBranch() const { return flags[IsMicroBranch]; }
     //@}
 
+    void setLastMicroop() { flags[IsLastMicroop] = true; }
     /// Operation class.  Used to select appropriate function unit in issue.
     OpClass opClass()     const { return _opClass; }
 };