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authorAndreas Hansson <andreas.hansson@arm.com>2016-01-11 05:52:20 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2016-01-11 05:52:20 -0500
commit12eb0343784f52994110df7e7fce4a0b639a6ec3 (patch)
tree12ff1c51b8051bb7e7d889eed499bee0dcd4cd1e /src/cpu
parent7661f1c2bf2b45603264076fabce2eb42373cd18 (diff)
downloadgem5-12eb0343784f52994110df7e7fce4a0b639a6ec3.tar.xz
scons: Enable -Wextra by default
Make best use of the compiler, and enable -Wextra as well as -Wall. There are a few issues that had to be resolved, but they are all trivial.
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/base_dyn_inst.hh6
-rw-r--r--src/cpu/pred/sat_counter.hh2
-rw-r--r--src/cpu/trace/trace_cpu.cc4
3 files changed, 6 insertions, 6 deletions
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 77117b892..ebe882a88 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -793,13 +793,13 @@ class BaseDynInst : public ExecContext, public RefCounted
void pcState(const TheISA::PCState &val) { pc = val; }
/** Read the PC of this instruction. */
- const Addr instAddr() const { return pc.instAddr(); }
+ Addr instAddr() const { return pc.instAddr(); }
/** Read the PC of the next instruction. */
- const Addr nextInstAddr() const { return pc.nextInstAddr(); }
+ Addr nextInstAddr() const { return pc.nextInstAddr(); }
/**Read the micro PC of this instruction. */
- const Addr microPC() const { return pc.microPC(); }
+ Addr microPC() const { return pc.microPC(); }
bool readPredicate()
{
diff --git a/src/cpu/pred/sat_counter.hh b/src/cpu/pred/sat_counter.hh
index 1294a4e08..4721a3f9f 100644
--- a/src/cpu/pred/sat_counter.hh
+++ b/src/cpu/pred/sat_counter.hh
@@ -105,7 +105,7 @@ class SatCounter
/**
* Read the counter's value.
*/
- const uint8_t read() const
+ uint8_t read() const
{ return counter; }
private:
diff --git a/src/cpu/trace/trace_cpu.cc b/src/cpu/trace/trace_cpu.cc
index f940be2f9..d6aa9aaeb 100644
--- a/src/cpu/trace/trace_cpu.cc
+++ b/src/cpu/trace/trace_cpu.cc
@@ -1337,8 +1337,8 @@ TraceCPU::ElasticDataGen::GraphNode::removeRegDep(NodeSeqNum reg_dep)
if (own_reg_dep == reg_dep) {
// If register dependency is found, make it zero and return true
own_reg_dep = 0;
+ assert(numRegDep > 0);
--numRegDep;
- assert(numRegDep >= 0);
DPRINTFR(TraceCPUData, "\tFor %lli: Marking register dependency %lli "
"done.\n", seqNum, reg_dep);
return true;
@@ -1356,8 +1356,8 @@ TraceCPU::ElasticDataGen::GraphNode::removeRobDep(NodeSeqNum rob_dep)
if (own_rob_dep == rob_dep) {
// If the rob dependency is found, make it zero and return true
own_rob_dep = 0;
+ assert(numRobDep > 0);
--numRobDep;
- assert(numRobDep >= 0);
DPRINTFR(TraceCPUData, "\tFor %lli: Marking ROB dependency %lli "
"done.\n", seqNum, rob_dep);
return true;