Registers: Add an ISA object which replaces the MiscRegFile.

This object encapsulates (or will eventually) the identity and characteristics
of the ISA in the CPU.

11 files changed, 98 insertions, 84 deletions

diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 3d7d713e8..51d62e179 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -168,7 +168,6 @@ InOrderCPU::InOrderCPU(Params *params)
       coreType("default"),
       _status(Idle),
       tickEvent(this),
-      miscRegFile(this),
       timeBuffer(2 , 2),
       removeInstsThisCycle(false),
       activityRec(params->name, NumStages, 10, params->activity),
@@ -267,15 +266,11 @@ InOrderCPU::InOrderCPU(Params *params)
 
         intRegFile[tid].clear();
         floatRegFile[tid].clear();
-    }
+        isa[tid].clear();
 
-    // Update miscRegFile if necessary
-    if (numThreads > 1) {
-        miscRegFile.expandForMultithreading(numThreads, numVirtProcs);
+        isa[tid].expandForMultithreading(numThreads, numVirtProcs);
     }
 
-    miscRegFile.clear();
-
     lastRunningCycle = curTick;
     contextSwitch = false;
 
@@ -461,7 +456,10 @@ InOrderCPU::readFunctional(Addr addr, uint32_t &buffer)
 void
 InOrderCPU::reset()
 {
-  miscRegFile.reset(coreType, numThreads, numVirtProcs, dynamic_cast<BaseCPU*>(this));
+    for (int i = 0; i < numThreads; i++) {
+        isa[i].reset(coreType, numThreads,
+                numVirtProcs, dynamic_cast<BaseCPU*>(this));
+    }
 }
 
 Port*
@@ -966,25 +964,25 @@ InOrderCPU::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
 MiscReg
 InOrderCPU::readMiscRegNoEffect(int misc_reg, ThreadID tid)
 {
-    return miscRegFile.readRegNoEffect(misc_reg, tid);
+    return isa[tid].readMiscRegNoEffect(misc_reg);
 }
 
 MiscReg
 InOrderCPU::readMiscReg(int misc_reg, ThreadID tid)
 {
-    return miscRegFile.readReg(misc_reg, tcBase(tid), tid);
+    return isa[tid].readMiscReg(misc_reg, tcBase(tid));
 }
 
 void
 InOrderCPU::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
 {
-    miscRegFile.setRegNoEffect(misc_reg, val, tid);
+    isa[tid].setMiscRegNoEffect(misc_reg, val);
 }
 
 void
 InOrderCPU::setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid)
 {
-    miscRegFile.setReg(misc_reg, val, tcBase(tid), tid);
+    isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
 }
 
 
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index 794d81def..bfc5139cf 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -39,6 +39,7 @@
 #include <vector>
 
 #include "arch/isa_traits.hh"
+#include "arch/types.hh"
 #include "base/statistics.hh"
 #include "base/timebuf.hh"
 #include "base/types.hh"
@@ -76,8 +77,8 @@ class InOrderCPU : public BaseCPU
     typedef TheISA::IntReg IntReg;
     typedef TheISA::FloatReg FloatReg;
     typedef TheISA::FloatRegBits FloatRegBits;
-    typedef TheISA::MiscReg MiscReg;
     typedef TheISA::RegFile RegFile;
+    typedef TheISA::MiscReg MiscReg;
 
     //DynInstPtr TypeDefs
     typedef ThePipeline::DynInstPtr DynInstPtr;
@@ -259,7 +260,9 @@ class InOrderCPU : public BaseCPU
     /** The Register File for the CPU */
     TheISA::IntRegFile intRegFile[ThePipeline::MaxThreads];;
     TheISA::FloatRegFile floatRegFile[ThePipeline::MaxThreads];;
-    TheISA::MiscRegFile miscRegFile;
+
+    /** ISA state */
+    TheISA::ISA isa[ThePipeline::MaxThreads];
 
     /** Dependency Tracker for Integer & Floating Point Regs */
     RegDepMap archRegDepMap[ThePipeline::MaxThreads];
diff --git a/src/cpu/inorder/thread_context.hh b/src/cpu/inorder/thread_context.hh
index f3cf3ec44..aac8901b3 100644
--- a/src/cpu/inorder/thread_context.hh
+++ b/src/cpu/inorder/thread_context.hh
@@ -211,6 +211,12 @@ class InOrderThreadContext : public ThreadContext
      * write might have as defined by the architecture. */
     virtual void setMiscReg(int misc_reg, const MiscReg &val);
 
+    virtual int flattenIntIndex(int reg)
+    { return cpu->isa[thread->readTid()].flattenIntIndex(reg); }
+
+    virtual int flattenFloatIndex(int reg)
+    { return cpu->isa[thread->readTid()].flattenFloatIndex(reg); }
+
     virtual void activateContext(int delay)
     { cpu->activateContext(thread->readTid(), delay); }
 
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 621b6c1b9..2f8869b6f 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1180,14 +1180,14 @@ template <class Impl>
 TheISA::MiscReg
 FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
 {
-    return this->regFile.readMiscRegNoEffect(misc_reg, tid);
+    return this->isa[tid].readMiscRegNoEffect(misc_reg);
 }
 
 template <class Impl>
 TheISA::MiscReg
 FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
 {
-    return this->regFile.readMiscReg(misc_reg, tid);
+    return this->isa[tid].readMiscReg(misc_reg, tcBase(tid));
 }
 
 template <class Impl>
@@ -1195,7 +1195,7 @@ void
 FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
         const TheISA::MiscReg &val, ThreadID tid)
 {
-    this->regFile.setMiscRegNoEffect(misc_reg, val, tid);
+    this->isa[tid].setMiscRegNoEffect(misc_reg, val);
 }
 
 template <class Impl>
@@ -1203,7 +1203,7 @@ void
 FullO3CPU<Impl>::setMiscReg(int misc_reg,
         const TheISA::MiscReg &val, ThreadID tid)
 {
-    this->regFile.setMiscReg(misc_reg, val, tid);
+    this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
 }
 
 template <class Impl>
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 5cf27df75..1289785dc 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -395,11 +395,11 @@ class FullO3CPU : public BaseO3CPU
 
     /** Get instruction asid. */
     int getInstAsid(ThreadID tid)
-    { return regFile.miscRegs[tid].getInstAsid(); }
+    { return isa[tid].instAsid(); }
 
     /** Get data asid. */
     int getDataAsid(ThreadID tid)
-    { return regFile.miscRegs[tid].getDataAsid(); }
+    { return isa[tid].dataAsid(); }
 #else
     /** Get instruction asid. */
     int getInstAsid(ThreadID tid)
@@ -603,6 +603,8 @@ class FullO3CPU : public BaseO3CPU
     /** Integer Register Scoreboard */
     Scoreboard scoreboard;
 
+    TheISA::ISA isa[Impl::MaxThreads];
+
   public:
     /** Enum to give each stage a specific index, so when calling
      *  activateStage() or deactivateStage(), they can specify which stage
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index 07f8d487b..e7b20e4a9 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -57,8 +57,6 @@ class PhysRegFile
     typedef TheISA::IntReg IntReg;
     typedef TheISA::FloatReg FloatReg;
     typedef TheISA::FloatRegBits FloatRegBits;
-    typedef TheISA::MiscRegFile MiscRegFile;
-    typedef TheISA::MiscReg MiscReg;
 
     typedef union {
         FloatReg d;
@@ -230,30 +228,6 @@ class PhysRegFile
         floatRegFile[reg_idx].q = val;
     }
 
-    MiscReg
-    readMiscRegNoEffect(int misc_reg, ThreadID tid)
-    {
-        return miscRegs[tid].readRegNoEffect(misc_reg);
-    }
-
-    MiscReg
-    readMiscReg(int misc_reg, ThreadID tid)
-    {
-        return miscRegs[tid].readReg(misc_reg, cpu->tcBase(tid));
-    }
-
-    void
-    setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
-    {
-        miscRegs[tid].setRegNoEffect(misc_reg, val);
-    }
-
-    void
-    setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid)
-    {
-        miscRegs[tid].setReg(misc_reg, val, cpu->tcBase(tid));
-    }
-
   public:
     /** (signed) integer register file. */
     IntReg *intRegFile;
@@ -261,9 +235,6 @@ class PhysRegFile
     /** Floating point register file. */
     PhysFloatReg *floatRegFile;
 
-    /** Miscellaneous register file. */
-    MiscRegFile miscRegs[Impl::MaxThreads];
-
 #if FULL_SYSTEM
   private:
     int intrflag;                       // interrupt flag
@@ -289,10 +260,6 @@ PhysRegFile<Impl>::PhysRegFile(O3CPU *_cpu, unsigned _numPhysicalIntRegs,
     intRegFile = new IntReg[numPhysicalIntRegs];
     floatRegFile = new PhysFloatReg[numPhysicalFloatRegs];
 
-    for (int i = 0; i < Impl::MaxThreads; ++i) {
-        miscRegs[i].clear();
-    }
-
     memset(intRegFile, 0, sizeof(IntReg) * numPhysicalIntRegs);
     memset(floatRegFile, 0, sizeof(PhysFloatReg) * numPhysicalFloatRegs);
 }
diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index 2bca6f81c..dd480f81c 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -959,11 +959,11 @@ DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid)
         RegIndex src_reg = inst->srcRegIdx(src_idx);
         RegIndex flat_src_reg = src_reg;
         if (src_reg < TheISA::FP_Base_DepTag) {
-            flat_src_reg = TheISA::flattenIntIndex(inst->tcBase(), src_reg);
+            flat_src_reg = inst->tcBase()->flattenIntIndex(src_reg);
             DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg);
         } else if (src_reg < TheISA::Ctrl_Base_DepTag) {
             src_reg = src_reg - TheISA::FP_Base_DepTag;
-            flat_src_reg = TheISA::flattenFloatIndex(inst->tcBase(), src_reg);
+            flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg);
             flat_src_reg += TheISA::NumIntRegs;
         } else {
             flat_src_reg = src_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs;
@@ -1009,7 +1009,7 @@ DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid)
         RegIndex flat_dest_reg = dest_reg;
         if (dest_reg < TheISA::FP_Base_DepTag) {
             // Integer registers are flattened.
-            flat_dest_reg = TheISA::flattenIntIndex(inst->tcBase(), dest_reg);
+            flat_dest_reg = inst->tcBase()->flattenIntIndex(dest_reg);
             DPRINTF(Rename, "Flattening index %d to %d.\n", (int)dest_reg, (int)flat_dest_reg);
         } else {
             // Floating point and Miscellaneous registers need their indexes
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index b10305d5d..a3f1ce58f 100755
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -226,6 +226,9 @@ class O3ThreadContext : public ThreadContext
      * write might have as defined by the architecture. */
     virtual void setMiscReg(int misc_reg, const MiscReg &val);
 
+    virtual int flattenIntIndex(int reg);
+    virtual int flattenFloatIndex(int reg);
+
     /** Returns the number of consecutive store conditional failures. */
     // @todo: Figure out where these store cond failures should go.
     virtual unsigned readStCondFailures()
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index bce334dc4..6527f5d06 100755
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -272,7 +272,7 @@ template <class Impl>
 uint64_t
 O3ThreadContext<Impl>::readIntReg(int reg_idx)
 {
-    reg_idx = TheISA::flattenIntIndex(this, reg_idx);
+    reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx);
     return cpu->readArchIntReg(reg_idx, thread->threadId());
 }
 
@@ -280,7 +280,7 @@ template <class Impl>
 TheISA::FloatReg
 O3ThreadContext<Impl>::readFloatReg(int reg_idx, int width)
 {
-    reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
+    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
     switch(width) {
       case 32:
         return cpu->readArchFloatRegSingle(reg_idx, thread->threadId());
@@ -296,7 +296,7 @@ template <class Impl>
 TheISA::FloatReg
 O3ThreadContext<Impl>::readFloatReg(int reg_idx)
 {
-    reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
+    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
     return cpu->readArchFloatRegSingle(reg_idx, thread->threadId());
 }
 
@@ -305,7 +305,7 @@ TheISA::FloatRegBits
 O3ThreadContext<Impl>::readFloatRegBits(int reg_idx, int width)
 {
     DPRINTF(Fault, "Reading floatint register through the TC!\n");
-    reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
+    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
     return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
 }
 
@@ -313,7 +313,7 @@ template <class Impl>
 TheISA::FloatRegBits
 O3ThreadContext<Impl>::readFloatRegBits(int reg_idx)
 {
-    reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
+    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
     return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
 }
 
@@ -321,7 +321,7 @@ template <class Impl>
 void
 O3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val)
 {
-    reg_idx = TheISA::flattenIntIndex(this, reg_idx);
+    reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx);
     cpu->setArchIntReg(reg_idx, val, thread->threadId());
 
     // Squash if we're not already in a state update mode.
@@ -334,7 +334,7 @@ template <class Impl>
 void
 O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val, int width)
 {
-    reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
+    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
     switch(width) {
       case 32:
         cpu->setArchFloatRegSingle(reg_idx, val, thread->threadId());
@@ -354,7 +354,7 @@ template <class Impl>
 void
 O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val)
 {
-    reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
+    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
     cpu->setArchFloatRegSingle(reg_idx, val, thread->threadId());
 
     if (!thread->trapPending && !thread->inSyscall) {
@@ -368,7 +368,7 @@ O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val,
                                              int width)
 {
     DPRINTF(Fault, "Setting floatint register through the TC!\n");
-    reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
+    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
     cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
 
     // Squash if we're not already in a state update mode.
@@ -381,7 +381,7 @@ template <class Impl>
 void
 O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
 {
-    reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
+    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
     cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
 
     // Squash if we're not already in a state update mode.
@@ -439,6 +439,20 @@ O3ThreadContext<Impl>::setNextMicroPC(uint64_t val)
 }
 
 template <class Impl>
+int
+O3ThreadContext<Impl>::flattenIntIndex(int reg)
+{
+    return cpu->isa[thread->threadId()].flattenIntIndex(reg);
+}
+
+template <class Impl>
+int
+O3ThreadContext<Impl>::flattenFloatIndex(int reg)
+{
+    return cpu->isa[thread->threadId()].flattenFloatIndex(reg);
+}
+
+template <class Impl>
 void
 O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
 {
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 08dd45640..3199263be 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -32,6 +32,7 @@
 #ifndef __CPU_SIMPLE_THREAD_HH__
 #define __CPU_SIMPLE_THREAD_HH__
 
+#include "arch/isa.hh"
 #include "arch/isa_traits.hh"
 #include "arch/regfile.hh"
 #include "arch/tlb.hh"
@@ -90,7 +91,6 @@ class SimpleThread : public ThreadState
   protected:
     typedef TheISA::RegFile RegFile;
     typedef TheISA::MachInst MachInst;
-    typedef TheISA::MiscRegFile MiscRegFile;
     typedef TheISA::MiscReg MiscReg;
     typedef TheISA::FloatReg FloatReg;
     typedef TheISA::FloatRegBits FloatRegBits;
@@ -99,6 +99,7 @@ class SimpleThread : public ThreadState
 
   protected:
     RegFile regs;       // correct-path register context
+    TheISA::ISA isa;    // one "instance" of the current ISA.
 
   public:
     // pointer to CPU associated with this SimpleThread
@@ -164,8 +165,8 @@ class SimpleThread : public ThreadState
     }
 
 #if FULL_SYSTEM
-    int getInstAsid() { return regs.instAsid(); }
-    int getDataAsid() { return regs.dataAsid(); }
+    int getInstAsid() { return isa.instAsid(); }
+    int getDataAsid() { return isa.dataAsid(); }
 
     void dumpFuncProfile();
 
@@ -229,61 +230,61 @@ class SimpleThread : public ThreadState
     //
     uint64_t readIntReg(int reg_idx)
     {
-        int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx);
+        int flatIndex = isa.flattenIntIndex(reg_idx);
         return regs.readIntReg(flatIndex);
     }
 
     FloatReg readFloatReg(int reg_idx, int width)
     {
-        int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+        int flatIndex = isa.flattenFloatIndex(reg_idx);
         return regs.readFloatReg(flatIndex, width);
     }
 
     FloatReg readFloatReg(int reg_idx)
     {
-        int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+        int flatIndex = isa.flattenFloatIndex(reg_idx);
         return regs.readFloatReg(flatIndex);
     }
 
     FloatRegBits readFloatRegBits(int reg_idx, int width)
     {
-        int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+        int flatIndex = isa.flattenFloatIndex(reg_idx);
         return regs.readFloatRegBits(flatIndex, width);
     }
 
     FloatRegBits readFloatRegBits(int reg_idx)
     {
-        int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+        int flatIndex = isa.flattenFloatIndex(reg_idx);
         return regs.readFloatRegBits(flatIndex);
     }
 
     void setIntReg(int reg_idx, uint64_t val)
     {
-        int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx);
+        int flatIndex = isa.flattenIntIndex(reg_idx);
         regs.setIntReg(flatIndex, val);
     }
 
     void setFloatReg(int reg_idx, FloatReg val, int width)
     {
-        int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+        int flatIndex = isa.flattenFloatIndex(reg_idx);
         regs.setFloatReg(flatIndex, val, width);
     }
 
     void setFloatReg(int reg_idx, FloatReg val)
     {
-        int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+        int flatIndex = isa.flattenFloatIndex(reg_idx);
         regs.setFloatReg(flatIndex, val);
     }
 
     void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
     {
-        int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+        int flatIndex = isa.flattenFloatIndex(reg_idx);
         regs.setFloatRegBits(flatIndex, val, width);
     }
 
     void setFloatRegBits(int reg_idx, FloatRegBits val)
     {
-        int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+        int flatIndex = isa.flattenFloatIndex(reg_idx);
         regs.setFloatRegBits(flatIndex, val);
     }
 
@@ -340,25 +341,37 @@ class SimpleThread : public ThreadState
     MiscReg
     readMiscRegNoEffect(int misc_reg, ThreadID tid = 0)
     {
-        return regs.readMiscRegNoEffect(misc_reg);
+        return isa.readMiscRegNoEffect(misc_reg);
     }
 
     MiscReg
     readMiscReg(int misc_reg, ThreadID tid = 0)
     {
-        return regs.readMiscReg(misc_reg, tc);
+        return isa.readMiscReg(misc_reg, tc);
     }
 
     void
     setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0)
     {
-        return regs.setMiscRegNoEffect(misc_reg, val);
+        return isa.setMiscRegNoEffect(misc_reg, val);
     }
 
     void
     setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0)
     {
-        return regs.setMiscReg(misc_reg, val, tc);
+        return isa.setMiscReg(misc_reg, val, tc);
+    }
+
+    int
+    flattenIntIndex(int reg)
+    {
+        return isa.flattenIntIndex(reg);
+    }
+
+    int
+    flattenFloatIndex(int reg)
+    {
+        return isa.flattenFloatIndex(reg);
     }
 
     unsigned readStCondFailures() { return storeCondFailures; }
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 3e37572d8..8963553d5 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -84,7 +84,6 @@ class ThreadContext
     typedef TheISA::IntReg IntReg;
     typedef TheISA::FloatReg FloatReg;
     typedef TheISA::FloatRegBits FloatRegBits;
-    typedef TheISA::MiscRegFile MiscRegFile;
     typedef TheISA::MiscReg MiscReg;
   public:
 
@@ -234,6 +233,9 @@ class ThreadContext
 
     virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
 
+    virtual int flattenIntIndex(int reg) = 0;
+    virtual int flattenFloatIndex(int reg) = 0;
+
     virtual uint64_t
     readRegOtherThread(int misc_reg, ThreadID tid)
     {
@@ -434,6 +436,12 @@ class ProxyThreadContext : public ThreadContext
     void setMiscReg(int misc_reg, const MiscReg &val)
     { return actualTC->setMiscReg(misc_reg, val); }
 
+    int flattenIntIndex(int reg)
+    { return actualTC->flattenIntIndex(reg); }
+
+    int flattenFloatIndex(int reg)
+    { return actualTC->flattenFloatIndex(reg); }
+
     unsigned readStCondFailures()
     { return actualTC->readStCondFailures(); }