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author | Ron Dreslinski <rdreslin@umich.edu> | 2006-11-14 18:41:37 -0500 |
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committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-11-14 18:41:37 -0500 |
commit | 4fbbb74a5c060110affdb235ce87bb53e2938b43 (patch) | |
tree | 4ba7a07006de173c2d1f24b240db53cf20e5f475 /src/cpu | |
parent | 7cd05a998d0090773f8fce4dab2b3b13a7f57ebb (diff) | |
parent | 069c7c30d1c871aba937a6a4ee7b1146d716ac4b (diff) | |
download | gem5-4fbbb74a5c060110affdb235ce87bb53e2938b43.tar.xz |
Merge zizzer:/bk/newmem
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
--HG--
extra : convert_revision : 8d61b474428d494b1a5382e4cf95934ad54e35dd
Diffstat (limited to 'src/cpu')
-rw-r--r-- | src/cpu/simple/timing.cc | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index d9839bede..3648f7613 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -290,6 +290,8 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags) // memory system takes ownership of packet dcache_pkt = NULL; } + } else { + delete req; } // This will need a new way to tell if it has a dcache attached. @@ -375,6 +377,8 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) dcache_pkt = NULL; } } + } else { + delete req; } // This will need a new way to tell if it's hooked up to a cache or not. @@ -457,6 +461,8 @@ TimingSimpleCPU::fetch() ifetch_pkt = NULL; } } else { + delete ifetch_req; + delete ifetch_pkt; // fetch fault: advance directly to next instruction (fault handler) advanceInst(fault); } @@ -490,13 +496,13 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt) _status = Running; - delete pkt->req; - delete pkt; - numCycles += curTick - previousTick; previousTick = curTick; if (getState() == SimObject::Draining) { + delete pkt->req; + delete pkt; + completeDrain(); return; } @@ -528,6 +534,9 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt) postExecute(); advanceInst(fault); } + + delete pkt->req; + delete pkt; } void |