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authorAli Saidi <saidi@eecs.umich.edu>2008-07-01 10:24:16 -0400
committerAli Saidi <saidi@eecs.umich.edu>2008-07-01 10:24:16 -0400
commit50e3e50e1ac592b357a47eecdc3c99a528172870 (patch)
tree1ee6c72dc10691ac920e793646e38c73049f3a8f /src/cpu
parent9bd0bfe559d8c9633c5686ccf100ab921eb6eda2 (diff)
downloadgem5-50e3e50e1ac592b357a47eecdc3c99a528172870.tar.xz
Make the cached virtPort have a thread context so it can do everything that a newly created one can.
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/o3/cpu.cc2
-rwxr-xr-xsrc/cpu/o3/thread_context.hh2
-rw-r--r--src/cpu/simple/atomic.cc2
-rw-r--r--src/cpu/simple/timing.cc2
-rw-r--r--src/cpu/thread_context.hh4
-rw-r--r--src/cpu/thread_state.cc8
-rw-r--r--src/cpu/thread_state.hh6
7 files changed, 13 insertions, 13 deletions
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index c75a08213..fac214174 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -788,7 +788,7 @@ FullO3CPU<Impl>::updateMemPorts()
// Update all ThreadContext's memory ports (Functional/Virtual
// Ports)
for (int i = 0; i < thread.size(); ++i)
- thread[i]->connectMemPorts();
+ thread[i]->connectMemPorts(thread[i]->getTC());
}
#endif
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index e7bdc6de5..44e26729c 100755
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -98,7 +98,7 @@ class O3ThreadContext : public ThreadContext
void delVirtPort(VirtualPort *vp);
- virtual void connectMemPorts() { thread->connectMemPorts(); }
+ virtual void connectMemPorts(ThreadContext *tc) { thread->connectMemPorts(tc); }
#else
virtual TranslatingPort *getMemPort() { return thread->getMemPort(); }
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 6b07502ef..0e04a36b2 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -148,7 +148,7 @@ AtomicSimpleCPU::DcachePort::setPeer(Port *port)
#if FULL_SYSTEM
// Update the ThreadContext's memory ports (Functional/Virtual
// Ports)
- cpu->tcBase()->connectMemPorts();
+ cpu->tcBase()->connectMemPorts(cpu->tcBase());
#endif
}
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 2cf7d584d..b86d4b2d7 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -766,7 +766,7 @@ TimingSimpleCPU::DcachePort::setPeer(Port *port)
#if FULL_SYSTEM
// Update the ThreadContext's memory ports (Functional/Virtual
// Ports)
- cpu->tcBase()->connectMemPorts();
+ cpu->tcBase()->connectMemPorts(cpu->tcBase());
#endif
}
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index cf51c1637..b25a67d59 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -134,7 +134,7 @@ class ThreadContext
virtual void delVirtPort(VirtualPort *vp) = 0;
- virtual void connectMemPorts() = 0;
+ virtual void connectMemPorts(ThreadContext *tc) = 0;
#else
virtual TranslatingPort *getMemPort() = 0;
@@ -325,7 +325,7 @@ class ProxyThreadContext : public ThreadContext
void delVirtPort(VirtualPort *vp) { return actualTC->delVirtPort(vp); }
- void connectMemPorts() { actualTC->connectMemPorts(); }
+ void connectMemPorts(ThreadContext *tc) { actualTC->connectMemPorts(tc); }
#else
TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
diff --git a/src/cpu/thread_state.cc b/src/cpu/thread_state.cc
index bcfc9c924..18845baf7 100644
--- a/src/cpu/thread_state.cc
+++ b/src/cpu/thread_state.cc
@@ -113,10 +113,10 @@ ThreadState::unserialize(Checkpoint *cp, const std::string &section)
#if FULL_SYSTEM
void
-ThreadState::connectMemPorts()
+ThreadState::connectMemPorts(ThreadContext *tc)
{
connectPhysPort();
- connectVirtPort();
+ connectVirtPort(tc);
}
void
@@ -134,7 +134,7 @@ ThreadState::connectPhysPort()
}
void
-ThreadState::connectVirtPort()
+ThreadState::connectVirtPort(ThreadContext *tc)
{
// @todo: For now this disregards any older port that may have
// already existed. Fix this memory leak once the bus port IDs
@@ -143,7 +143,7 @@ ThreadState::connectVirtPort()
virtPort->removeConn();
else
virtPort = new VirtualPort(csprintf("%s-%d-vport",
- baseCpu->name(), tid));
+ baseCpu->name(), tid), tc);
connectToMemFunc(virtPort);
}
diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh
index 4f878db1f..b6a62eebc 100644
--- a/src/cpu/thread_state.hh
+++ b/src/cpu/thread_state.hh
@@ -91,11 +91,11 @@ struct ThreadState {
Tick readLastSuspend() { return lastSuspend; }
#if FULL_SYSTEM
- void connectMemPorts();
+ void connectMemPorts(ThreadContext *tc);
void connectPhysPort();
- void connectVirtPort();
+ void connectVirtPort(ThreadContext *tc);
void dumpFuncProfile();
@@ -201,7 +201,7 @@ struct ThreadState {
FunctionalPort *physPort;
/** A functional port, outgoing only, for functional accesse to virtual
- * addresses. That doen't require execution context information */
+ * addresses. */
VirtualPort *virtPort;
#else
TranslatingPort *port;