cpu: Replace the fastmem with a new CPU model

The AtomicSimpleCPU used to be able to access memory directly to speed
up simulation if no caches are used. This is fine as long as no
switching between CPU models is required. In order to switch to a new
CPU model that requires caches, we currently need to checkpoint the
system and restore it into a new configuration. The new
'atomic_noncaching' memory mode provides a solution that avoids this
issue since caches are bypassed in this mode. This changeset removes
the old fastmem option from the AtomicSimpleCPU and introduces a new
CPU, NonCachingSimpleCPU, which derives from the AtomicSimpleCPU.

The NonCachingSimpleCPU uses the same mechanism as the AtomicSimpleCPU
used to use when accessing memory in when fastmem was enabled.

This changeset also introduces a new switcheroo test that tests
switching between a NonCachingSimpleCPU and a TimingSimpleCPU with
caches.

Change-Id: If01893f9b37528b14f530c11ce6f53c097582c21
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12419
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

7 files changed, 218 insertions, 21 deletions

diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py
index 04592c68a..15a3feb69 100644
--- a/src/cpu/simple/AtomicSimpleCPU.py
+++ b/src/cpu/simple/AtomicSimpleCPU.py
@@ -61,7 +61,6 @@ class AtomicSimpleCPU(BaseSimpleCPU):
     width = Param.Int(1, "CPU width")
     simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles")
     simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles")
-    fastmem = Param.Bool(False, "Access memory directly")
 
     def addSimPointProbe(self, interval):
         simpoint = SimPoint()
diff --git a/src/cpu/simple/NonCachingSimpleCPU.py b/src/cpu/simple/NonCachingSimpleCPU.py
new file mode 100644
index 000000000..2905a79ac
--- /dev/null
+++ b/src/cpu/simple/NonCachingSimpleCPU.py
@@ -0,0 +1,60 @@
+# Copyright (c) 2012, 2018 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+from m5.params import *
+from AtomicSimpleCPU import AtomicSimpleCPU
+
+class NonCachingSimpleCPU(AtomicSimpleCPU):
+    """Simple CPU model based on the atomic CPU. Unlike the atomic CPU,
+    this model causes the memory system to bypass caches and is
+    therefore slightly faster in some cases. However, its main purpose
+    is as a substitute for hardware virtualized CPUs when
+    stress-testing the memory system.
+
+    """
+
+    type = 'NonCachingSimpleCPU'
+    cxx_header = "cpu/simple/noncaching.hh"
+
+    @classmethod
+    def memory_mode(cls):
+        return 'atomic_noncaching'
+
+    @classmethod
+    def support_take_over(cls):
+        return True
+
diff --git a/src/cpu/simple/SConscript b/src/cpu/simple/SConscript
index 3b6b19c51..991519c6e 100644
--- a/src/cpu/simple/SConscript
+++ b/src/cpu/simple/SConscript
@@ -36,6 +36,12 @@ if 'AtomicSimpleCPU' in env['CPU_MODELS']:
     SimObject('AtomicSimpleCPU.py')
     Source('atomic.cc')
 
+    # The NonCachingSimpleCPU is really an atomic CPU in
+    # disguise. It's therefore always enabled when the atomic CPU is
+    # enabled.
+    SimObject('NonCachingSimpleCPU.py')
+    Source('noncaching.cc')
+
 if 'TimingSimpleCPU' in env['CPU_MODELS']:
     need_simple_base = True
     SimObject('TimingSimpleCPU.py')
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 040d1dbf9..e91fafbcc 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -1,6 +1,6 @@
 /*
  * Copyright 2014 Google, Inc.
- * Copyright (c) 2012-2013,2015,2017 ARM Limited
+ * Copyright (c) 2012-2013,2015,2017-2018 ARM Limited
  * All rights reserved.
  *
  * The license below extends only to copyright in the software and shall
@@ -83,7 +83,7 @@ AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
       simulate_inst_stalls(p->simulate_inst_stalls),
       icachePort(name() + ".icache_port", this),
       dcachePort(name() + ".dcache_port", this),
-      fastmem(p->fastmem), dcache_access(false), dcache_latency(0),
+      dcache_access(false), dcache_latency(0),
       ppCommit(nullptr)
 {
     _status = Idle;
@@ -271,6 +271,11 @@ AtomicSimpleCPU::suspendContext(ThreadID thread_num)
     BaseCPU::suspendContext(thread_num);
 }
 
+Tick
+AtomicSimpleCPU::sendPacket(MasterPort &port, const PacketPtr &pkt)
+{
+    return port.sendAtomic(pkt);
+}
 
 Tick
 AtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(PacketPtr pkt)
@@ -364,13 +369,10 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t * data, unsigned size,
             Packet pkt(req, Packet::makeReadCmd(req));
             pkt.dataStatic(data);
 
-            if (req->isMmappedIpr())
+            if (req->isMmappedIpr()) {
                 dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt);
-            else {
-                if (fastmem && system->isMemAddr(pkt.getAddr()))
-                    system->getPhysMem().access(&pkt);
-                else
-                    dcache_latency += dcachePort.sendAtomic(&pkt);
+            } else {
+                dcache_latency += sendPacket(dcachePort, &pkt);
             }
             dcache_access = true;
 
@@ -483,10 +485,7 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, Addr addr,
                     dcache_latency +=
                         TheISA::handleIprWrite(thread->getTC(), &pkt);
                 } else {
-                    if (fastmem && system->isMemAddr(pkt.getAddr()))
-                        system->getPhysMem().access(&pkt);
-                    else
-                        dcache_latency += dcachePort.sendAtomic(&pkt);
+                    dcache_latency += sendPacket(dcachePort, &pkt);
 
                     // Notify other threads on this CPU of write
                     threadSnoop(&pkt, curThread);
@@ -603,10 +602,7 @@ AtomicSimpleCPU::tick()
                     Packet ifetch_pkt = Packet(ifetch_req, MemCmd::ReadReq);
                     ifetch_pkt.dataStatic(&inst);
 
-                    if (fastmem && system->isMemAddr(ifetch_pkt.getAddr()))
-                        system->getPhysMem().access(&ifetch_pkt);
-                    else
-                        icache_latency = icachePort.sendAtomic(&ifetch_pkt);
+                    icache_latency = sendPacket(icachePort, &ifetch_pkt);
 
                     assert(!ifetch_pkt.isError());
 
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index addbe234e..a5151aa18 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2013,2015 ARM Limited
+ * Copyright (c) 2012-2013, 2015, 2018 ARM Limited
  * All rights reserved.
  *
  * The license below extends only to copyright in the software and shall
@@ -58,7 +58,7 @@ class AtomicSimpleCPU : public BaseSimpleCPU
 
     void init() override;
 
-  private:
+  protected:
 
     EventFunctionWrapper tickEvent;
 
@@ -103,6 +103,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU
      */
     bool tryCompleteDrain();
 
+    virtual Tick sendPacket(MasterPort &port, const PacketPtr &pkt);
+
     /**
      * An AtomicCPUPort overrides the default behaviour of the
      * recvAtomicSnoop and ignores the packet instead of panicking. It
@@ -137,7 +139,6 @@ class AtomicSimpleCPU : public BaseSimpleCPU
     {
 
       public:
-
         AtomicCPUDPort(const std::string &_name, BaseSimpleCPU* _cpu)
             : AtomicCPUPort(_name, _cpu), cpu(_cpu)
         {
@@ -158,7 +159,7 @@ class AtomicSimpleCPU : public BaseSimpleCPU
     AtomicCPUPort icachePort;
     AtomicCPUDPort dcachePort;
 
-    bool fastmem;
+
     RequestPtr ifetch_req;
     RequestPtr data_read_req;
     RequestPtr data_write_req;
diff --git a/src/cpu/simple/noncaching.cc b/src/cpu/simple/noncaching.cc
new file mode 100644
index 000000000..335d38b0c
--- /dev/null
+++ b/src/cpu/simple/noncaching.cc
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2012, 2018 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Andreas Sandberg
+ */
+
+#include "cpu/simple/noncaching.hh"
+
+NonCachingSimpleCPU::NonCachingSimpleCPU(NonCachingSimpleCPUParams *p)
+    : AtomicSimpleCPU(p)
+{
+}
+
+void
+NonCachingSimpleCPU::verifyMemoryMode() const
+{
+    if (!(system->isAtomicMode() && system->bypassCaches())) {
+        fatal("The direct CPU requires the memory system to be in the "
+              "'atomic_noncaching' mode.\n");
+    }
+}
+
+Tick
+NonCachingSimpleCPU::sendPacket(MasterPort &port, const PacketPtr &pkt)
+{
+    if (system->isMemAddr(pkt->getAddr())) {
+        system->getPhysMem().access(pkt);
+        return 0;
+    } else {
+        return port.sendAtomic(pkt);
+    }
+}
+
+NonCachingSimpleCPU *
+NonCachingSimpleCPUParams::create()
+{
+    numThreads = 1;
+    if (!FullSystem && workload.size() != 1)
+        fatal("only one workload allowed");
+    return new NonCachingSimpleCPU(this);
+}
diff --git a/src/cpu/simple/noncaching.hh b/src/cpu/simple/noncaching.hh
new file mode 100644
index 000000000..775aa2155
--- /dev/null
+++ b/src/cpu/simple/noncaching.hh
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2012, 2018 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Andreas Sandberg
+ */
+
+#ifndef __CPU_SIMPLE_NONCACHING_HH__
+#define __CPU_SIMPLE_NONCACHING_HH___
+
+#include "cpu/simple/atomic.hh"
+#include "params/NonCachingSimpleCPU.hh"
+
+/**
+ * The NonCachingSimpleCPU is an AtomicSimpleCPU using the
+ * 'atomic_noncaching' memory mode instead of just 'atomic'.
+ */
+class NonCachingSimpleCPU : public AtomicSimpleCPU
+{
+  public:
+    NonCachingSimpleCPU(NonCachingSimpleCPUParams *p);
+
+    void verifyMemoryMode() const override;
+
+  protected:
+    Tick sendPacket(MasterPort &port, const PacketPtr &pkt) override;
+};
+
+#endif // __CPU_SIMPLE_NONCACHING_HH__