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authorHanhwi Jang <jang.hanhwi@gmail.com>2018-01-20 23:55:27 +0900
committerHanhwi Jang <jang.hanhwi@gmail.com>2018-07-24 00:52:51 +0000
commitcfc3a3a628a4de7e0da8287351c5f37a5c053e14 (patch)
tree018e6b6def43b41caae26932924db5ab3ced4dff /src/cpu
parent385f799fe23928cfd15580c3ad2a034119c5648e (diff)
downloadgem5-cfc3a3a628a4de7e0da8287351c5f37a5c053e14.tar.xz
cpu-o3: Missing freeing the heads of DepGraph in IQ squashing
Free the squahsed instructions' heads of DepGraph in IQ squashing In a system with large register file (ex.2048), the number of DynInst hits the hardcoded limit (1500). This is caused by missing freeing the heads of DepGraph in IQ. IQ only clears out the heads when instructions reach writeback stage. If a instruction is squashed before writeback stage, its head of dependency graph, which holds the instruction's DynInstPtr, would not be cleared out. This prevents freeing the DynInst of the squahsed instruction even after it is committed. Change-Id: I05b3db93cb6ad8960183d7ae765149c7f292e5b3 Reviewed-on: https://gem5-review.googlesource.com/7481 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/o3/inst_queue_impl.hh19
1 files changed, 19 insertions, 0 deletions
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index f70f66274..84ac5799c 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -1338,6 +1338,25 @@ InstructionQueue<Impl>::doSquash(ThreadID tid)
++freeEntries;
}
+ // IQ clears out the heads of the dependency graph only when
+ // instructions reach writeback stage. If an instruction is squashed
+ // before writeback stage, its head of dependency graph would not be
+ // cleared out; it holds the instruction's DynInstPtr. This prevents
+ // freeing the squashed instruction's DynInst.
+ // Thus, we need to manually clear out the squashed instructions' heads
+ // of dependency graph.
+ for (int dest_reg_idx = 0;
+ dest_reg_idx < squashed_inst->numDestRegs();
+ dest_reg_idx++)
+ {
+ PhysRegIdPtr dest_reg =
+ squashed_inst->renamedDestRegIdx(dest_reg_idx);
+ if (dest_reg->isFixedMapping()){
+ continue;
+ }
+ assert(dependGraph.empty(dest_reg->flatIndex()));
+ dependGraph.clearInst(dest_reg->flatIndex());
+ }
instList[tid].erase(squash_it--);
++iqSquashedInstsExamined;
}