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authorGabe Black <gblack@eecs.umich.edu>2008-06-12 00:35:50 -0400
committerGabe Black <gblack@eecs.umich.edu>2008-06-12 00:35:50 -0400
commitd093fcb07924cc4341b8142c448b905dd94f7125 (patch)
treed6d23a7156c040690f54783382282ea19169a822 /src/cpu
parent5797ff10160df8fa9f51196753ab702cf190163f (diff)
downloadgem5-d093fcb07924cc4341b8142c448b905dd94f7125.tar.xz
CPU: Make the simple cpu trace data for loads/stores.
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/simple/atomic.cc6
-rw-r--r--src/cpu/simple/timing.cc6
2 files changed, 12 insertions, 0 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 23bd40b9b..acd280568 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -355,6 +355,9 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
if (secondAddr <= addr)
{
data = gtoh(data);
+ if (traceData) {
+ traceData->setData(data);
+ }
return fault;
}
@@ -568,6 +571,9 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
// If the write needs to have a fault on the access, consider
// calling changeStatus() and changing it to "bad addr write"
// or something.
+ if (traceData) {
+ traceData->setData(data);
+ }
return fault;
}
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index a76824ff3..d0c7dd787 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -296,6 +296,9 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
delete req;
}
+ if (traceData) {
+ traceData->setData(data);
+ }
return fault;
}
@@ -431,6 +434,9 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
delete req;
}
+ if (traceData) {
+ traceData->setData(data);
+ }
// If the write needs to have a fault on the access, consider calling
// changeStatus() and changing it to "bad addr write" or something.