Rename cycles() function to ticks()

--HG--
extra : convert_revision : 790eddb793d4f5ba35813d001037bd8601bd76a5

15 files changed, 32 insertions, 32 deletions

diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 7b31eb766..25bd3f893 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -74,7 +74,7 @@ CPUProgressEvent::process()
 {
     Counter temp = cpu->totalInstructions();
 #ifndef NDEBUG
-    double ipc = double(temp - lastNumInst) / (interval / cpu->cycles(1));
+    double ipc = double(temp - lastNumInst) / (interval / cpu->ticks(1));
 
     DPRINTFN("%s progress event, instructions committed: %lli, IPC: %0.8d\n",
              cpu->name(), temp - lastNumInst, ipc);
@@ -223,7 +223,7 @@ BaseCPU::startup()
 
     if (params->progress_interval) {
         new CPUProgressEvent(&mainEventQueue,
-                             cycles(params->progress_interval),
+                             ticks(params->progress_interval),
                              this);
     }
 }
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 6f4158d47..3c3e91523 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -82,7 +82,7 @@ class BaseCPU : public MemObject
   public:
 //    Tick currentTick;
     inline Tick frequency() const { return Clock::Frequency / clock; }
-    inline Tick cycles(int numCycles) const { return clock * numCycles; }
+    inline Tick ticks(int numCycles) const { return clock * numCycles; }
     inline Tick curCycle() const { return curTick / clock; }
     inline Tick tickToCycles(Tick val) const { return val / clock; }
     // @todo remove me after debugging with legion done
diff --git a/src/cpu/memtest/memtest.cc b/src/cpu/memtest/memtest.cc
index 583fd5f8d..f8c8a0547 100644
--- a/src/cpu/memtest/memtest.cc
+++ b/src/cpu/memtest/memtest.cc
@@ -270,7 +270,7 @@ void
 MemTest::tick()
 {
     if (!tickEvent.scheduled())
-        tickEvent.schedule(curTick + cycles(1));
+        tickEvent.schedule(curTick + ticks(1));
 
     if (++noResponseCycles >= 500000) {
         cerr << name() << ": deadlocked at cycle " << curTick << endl;
diff --git a/src/cpu/memtest/memtest.hh b/src/cpu/memtest/memtest.hh
index fa168c70b..1c918df33 100644
--- a/src/cpu/memtest/memtest.hh
+++ b/src/cpu/memtest/memtest.hh
@@ -55,7 +55,7 @@ class MemTest : public MemObject
     // register statistics
     virtual void regStats();
 
-    inline Tick cycles(int numCycles) const { return numCycles; }
+    inline Tick ticks(int numCycles) const { return numCycles; }
 
     // main simulation loop (one cycle)
     void tick();
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index f263383ae..e32dc7921 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -325,7 +325,7 @@ DefaultCommit<Impl>::initStage()
     cpu->activateStage(O3CPU::CommitIdx);
 
     cpu->activityThisCycle();
-    trapLatency = cpu->cycles(trapLatency);
+    trapLatency = cpu->ticks(trapLatency);
 }
 
 template <class Impl>
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index b2b7e09c0..3842d27bd 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -464,7 +464,7 @@ FullO3CPU<Impl>::tick()
             lastRunningCycle = curTick;
             timesIdled++;
         } else {
-            tickEvent.schedule(nextCycle(curTick + cycles(1)));
+            tickEvent.schedule(nextCycle(curTick + ticks(1)));
             DPRINTF(O3CPU, "Scheduling next tick!\n");
         }
     }
@@ -558,7 +558,7 @@ FullO3CPU<Impl>::activateContext(int tid, int delay)
     // Needs to set each stage to running as well.
     if (delay){
         DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
-                "on cycle %d\n", tid, curTick + cycles(delay));
+                "on cycle %d\n", tid, curTick + ticks(delay));
         scheduleActivateThreadEvent(tid, delay);
     } else {
         activateThread(tid);
@@ -585,7 +585,7 @@ FullO3CPU<Impl>::deallocateContext(int tid, bool remove, int delay)
     // Schedule removal of thread data from CPU
     if (delay){
         DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate "
-                "on cycle %d\n", tid, curTick + cycles(delay));
+                "on cycle %d\n", tid, curTick + ticks(delay));
         scheduleDeallocateContextEvent(tid, remove, delay);
         return false;
     } else {
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index d97a2080d..162e377e1 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -146,9 +146,9 @@ class FullO3CPU : public BaseO3CPU
     void scheduleTickEvent(int delay)
     {
         if (tickEvent.squashed())
-            tickEvent.reschedule(nextCycle(curTick + cycles(delay)));
+            tickEvent.reschedule(nextCycle(curTick + ticks(delay)));
         else if (!tickEvent.scheduled())
-            tickEvent.schedule(nextCycle(curTick + cycles(delay)));
+            tickEvent.schedule(nextCycle(curTick + ticks(delay)));
     }
 
     /** Unschedule tick event, regardless of its current state. */
@@ -187,10 +187,10 @@ class FullO3CPU : public BaseO3CPU
         // Schedule thread to activate, regardless of its current state.
         if (activateThreadEvent[tid].squashed())
             activateThreadEvent[tid].
-                reschedule(nextCycle(curTick + cycles(delay)));
+                reschedule(nextCycle(curTick + ticks(delay)));
         else if (!activateThreadEvent[tid].scheduled())
             activateThreadEvent[tid].
-                schedule(nextCycle(curTick + cycles(delay)));
+                schedule(nextCycle(curTick + ticks(delay)));
     }
 
     /** Unschedule actiavte thread event, regardless of its current state. */
@@ -238,10 +238,10 @@ class FullO3CPU : public BaseO3CPU
         // Schedule thread to activate, regardless of its current state.
         if (deallocateContextEvent[tid].squashed())
             deallocateContextEvent[tid].
-                reschedule(nextCycle(curTick + cycles(delay)));
+                reschedule(nextCycle(curTick + ticks(delay)));
         else if (!deallocateContextEvent[tid].scheduled())
             deallocateContextEvent[tid].
-                schedule(nextCycle(curTick + cycles(delay)));
+                schedule(nextCycle(curTick + ticks(delay)));
     }
 
     /** Unschedule thread deallocation in CPU */
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index 47f019ebe..aea62f12d 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -752,7 +752,7 @@ InstructionQueue<Impl>::scheduleReadyInsts()
                 FUCompletion *execution = new FUCompletion(issuing_inst,
                                                            idx, this);
 
-                execution->schedule(curTick + cpu->cycles(issue_latency - 1));
+                execution->schedule(curTick + cpu->ticks(issue_latency - 1));
 
                 // @todo: Enforce that issue_latency == 1 or op_latency
                 if (issue_latency > 1) {
diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index 78d0892c4..036db1351 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -315,9 +315,9 @@ class OzoneCPU : public BaseCPU
     void scheduleTickEvent(int delay)
     {
         if (tickEvent.squashed())
-            tickEvent.reschedule(curTick + cycles(delay));
+            tickEvent.reschedule(curTick + ticks(delay));
         else if (!tickEvent.scheduled())
-            tickEvent.schedule(curTick + cycles(delay));
+            tickEvent.schedule(curTick + ticks(delay));
     }
 
     /// Unschedule tick event, regardless of its current state.
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index 37a91c630..5080c54f6 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -613,7 +613,7 @@ OzoneCPU<Impl>::tick()
     comInstEventQueue[0]->serviceEvents(numInst);
 
     if (!tickEvent.scheduled() && _status == Running)
-        tickEvent.schedule(curTick + cycles(1));
+        tickEvent.schedule(curTick + ticks(1));
 }
 
 template <class Impl>
diff --git a/src/cpu/ozone/lw_back_end_impl.hh b/src/cpu/ozone/lw_back_end_impl.hh
index f84bda348..42788cee1 100644
--- a/src/cpu/ozone/lw_back_end_impl.hh
+++ b/src/cpu/ozone/lw_back_end_impl.hh
@@ -45,7 +45,7 @@ LWBackEnd<Impl>::generateTrapEvent(Tick latency)
 
     TrapEvent *trap = new TrapEvent(this);
 
-    trap->schedule(curTick + cpu->cycles(latency));
+    trap->schedule(curTick + cpu->ticks(latency));
 
     thread->trapPending = true;
 }
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 06f52e30e..9187fa7c7 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -254,7 +254,7 @@ AtomicSimpleCPU::activateContext(int thread_num, int delay)
     notIdleFraction++;
 
     //Make sure ticks are still on multiples of cycles
-    tickEvent.schedule(nextCycle(curTick + cycles(delay)));
+    tickEvent.schedule(nextCycle(curTick + ticks(delay)));
     _status = Running;
 }
 
@@ -584,7 +584,7 @@ AtomicSimpleCPU::tick()
 {
     DPRINTF(SimpleCPU, "Tick\n");
 
-    Tick latency = cycles(1); // instruction takes one cycle by default
+    Tick latency = ticks(1); // instruction takes one cycle by default
 
     for (int i = 0; i < width; ++i) {
         numCycles++;
@@ -642,14 +642,14 @@ AtomicSimpleCPU::tick()
 
             if (simulate_stalls) {
                 Tick icache_stall =
-                    icache_access ? icache_latency - cycles(1) : 0;
+                    icache_access ? icache_latency - ticks(1) : 0;
                 Tick dcache_stall =
-                    dcache_access ? dcache_latency - cycles(1) : 0;
-                Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1);
-                if (cycles(stall_cycles) < (icache_stall + dcache_stall))
-                    latency += cycles(stall_cycles+1);
+                    dcache_access ? dcache_latency - ticks(1) : 0;
+                Tick stall_cycles = (icache_stall + dcache_stall) / ticks(1);
+                if (ticks(stall_cycles) < (icache_stall + dcache_stall))
+                    latency += ticks(stall_cycles+1);
                 else
-                    latency += cycles(stall_cycles);
+                    latency += ticks(stall_cycles);
             }
 
         }
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index eee5b8cb5..2b5577e04 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -222,7 +222,7 @@ TimingSimpleCPU::activateContext(int thread_num, int delay)
     _status = Running;
 
     // kick things off by initiating the fetch of the next instruction
-    fetchEvent = new FetchEvent(this, nextCycle(curTick + cycles(delay)));
+    fetchEvent = new FetchEvent(this, nextCycle(curTick + ticks(delay)));
 }
 
 
diff --git a/src/cpu/trace/trace_cpu.cc b/src/cpu/trace/trace_cpu.cc
index e5739b2ce..d3cf34e9d 100644
--- a/src/cpu/trace/trace_cpu.cc
+++ b/src/cpu/trace/trace_cpu.cc
@@ -110,10 +110,10 @@ TraceCPU::tick()
         if (mainEventQueue.empty()) {
             exitSimLoop("end of memory trace reached");
         } else {
-            tickEvent.schedule(mainEventQueue.nextEventTime() + cycles(1));
+            tickEvent.schedule(mainEventQueue.nextEventTime() + ticks(1));
         }
     } else {
-        tickEvent.schedule(max(curTick + cycles(1), nextCycle));
+        tickEvent.schedule(max(curTick + ticks(1), nextCycle));
     }
 }
 
diff --git a/src/cpu/trace/trace_cpu.hh b/src/cpu/trace/trace_cpu.hh
index 9c96d71d5..b88c7072e 100644
--- a/src/cpu/trace/trace_cpu.hh
+++ b/src/cpu/trace/trace_cpu.hh
@@ -107,7 +107,7 @@ class TraceCPU : public SimObject
              MemInterface *dcache_interface,
              MemTraceReader *data_trace);
 
-    inline Tick cycles(int numCycles) { return numCycles; }
+    inline Tick ticks(int numCycles) { return numCycles; }
 
     /**
      * Perform all the accesses for one cycle.