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authorAndreas Sandberg <andreas.sandberg@arm.com>2015-11-20 14:50:17 -0600
committerAndreas Sandberg <andreas.sandberg@arm.com>2015-11-20 14:50:17 -0600
commitd57a855e40e5d85024ce4a5dd31ad1e45897ee04 (patch)
tree8d7ce03cd66781f7b2b08993897b65bedecbe133 /src/cpu
parent90d430d5b3e0e322c07270bb168653eb4f5b2713 (diff)
downloadgem5-d57a855e40e5d85024ce4a5dd31ad1e45897ee04.tar.xz
cpu: Enforce 1 interrupt controller per thread
Consider it a fatal configuration error if the number of interrupt controllers doesn't match the number of threads in an SMT configuration.
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/base.cc14
1 files changed, 6 insertions, 8 deletions
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index a1dfa42ce..9ba7e08a7 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -237,14 +237,12 @@ BaseCPU::BaseCPU(Params *p, bool is_checker)
// The interrupts should always be present unless this CPU is
// switched in later or in case it is a checker CPU
if (!params()->switched_out && !is_checker) {
- if (!interrupts.empty()) {
- for (ThreadID tid = 0; tid < numThreads; tid++) {
- interrupts[tid]->setCPU(this);
- }
- } else {
- fatal("CPU %s has no interrupt controller.\n"
- "Ensure createInterruptController() is called.\n", name());
- }
+ fatal_if(interrupts.size() != numThreads,
+ "CPU %s has %i interrupt controllers, but is expecting one "
+ "per thread (%i)\n",
+ name(), interrupts.size(), numThreads);
+ for (ThreadID tid = 0; tid < numThreads; tid++)
+ interrupts[tid]->setCPU(this);
}
if (FullSystem) {