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authorSteve Reinhardt <stever@eecs.umich.edu>2006-05-31 00:12:29 -0400
committerSteve Reinhardt <stever@eecs.umich.edu>2006-05-31 00:12:29 -0400
commitd77d39daee5c3ba8483d58911a1d5b12c4707040 (patch)
tree55b0fd6943a73d115d6dccad29ff875b60d65726 /src/cpu
parent91e3aa629550fcdaa03173f94674a74ac906ae4c (diff)
downloadgem5-d77d39daee5c3ba8483d58911a1d5b12c4707040.tar.xz
Streamline interface to Request object.
src/SConscript: mem/request.cc no longer needed (all functions inline). src/cpu/simple/atomic.cc: src/cpu/simple/base.cc: src/cpu/simple/timing.cc: src/dev/io_device.cc: src/mem/port.cc: Modified Request object interface. src/mem/packet.hh: Modified Request object interface. Address & size are always set together now, so track with single flag. src/mem/request.hh: Streamline interface to support a handful of calls that set multiple fields reflecting common usage patterns. Reduce number of validFoo booleans by combining flags for fields which must be set together. --HG-- extra : convert_revision : 3b499de90d6d5f12f0cc7a9a788663265677fe10
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/simple/atomic.cc28
-rw-r--r--src/cpu/simple/base.cc10
-rw-r--r--src/cpu/simple/timing.cc20
3 files changed, 17 insertions, 41 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index c2e6f6185..99b022c07 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -120,26 +120,17 @@ AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
{
_status = Idle;
- ifetch_req = new Request(true);
- ifetch_req->setAsid(0);
- // @todo fix me and get the real cpu iD!!!
- ifetch_req->setCpuNum(0);
- ifetch_req->setSize(sizeof(MachInst));
+ // @todo fix me and get the real cpu id & thread number!!!
+ ifetch_req = new Request();
ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
ifetch_pkt->dataStatic(&inst);
- data_read_req = new Request(true);
- // @todo fix me and get the real cpu iD!!!
- data_read_req->setCpuNum(0);
- data_read_req->setAsid(0);
+ data_read_req = new Request();
data_read_pkt = new Packet(data_read_req, Packet::ReadReq,
Packet::Broadcast);
data_read_pkt->dataStatic(&dataReg);
- data_write_req = new Request(true);
- // @todo fix me and get the real cpu iD!!!
- data_write_req->setCpuNum(0);
- data_write_req->setAsid(0);
+ data_write_req = new Request();
data_write_pkt = new Packet(data_write_req, Packet::WriteReq,
Packet::Broadcast);
}
@@ -236,10 +227,7 @@ template <class T>
Fault
AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
{
- data_read_req->setVaddr(addr);
- data_read_req->setSize(sizeof(T));
- data_read_req->setFlags(flags);
- data_read_req->setTime(curTick);
+ data_read_req->setVirt(0, addr, sizeof(T), flags, cpuXC->readPC());
if (traceData) {
traceData->setAddr(addr);
@@ -314,10 +302,7 @@ template <class T>
Fault
AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
{
- data_write_req->setVaddr(addr);
- data_write_req->setTime(curTick);
- data_write_req->setSize(sizeof(T));
- data_write_req->setFlags(flags);
+ data_write_req->setVirt(0, addr, sizeof(T), flags, cpuXC->readPC());
if (traceData) {
traceData->setAddr(addr);
@@ -408,7 +393,6 @@ AtomicSimpleCPU::tick()
checkForInterrupts();
- ifetch_req->resetMin();
Fault fault = setupFetchRequest(ifetch_req);
if (fault == NoFault) {
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 2e9b4b81f..2e979870c 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -357,13 +357,9 @@ BaseSimpleCPU::setupFetchRequest(Request *req)
DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",cpuXC->readPC(),
cpuXC->readNextPC(),cpuXC->readNextNPC());
- req->setVaddr(cpuXC->readPC() & ~3);
- req->setTime(curTick);
-#if FULL_SYSTEM
- req->setFlags((cpuXC->readPC() & 1) ? PHYSICAL : 0);
-#else
- req->setFlags(0);
-#endif
+ req->setVirt(0, cpuXC->readPC() & ~3, sizeof(MachInst),
+ (FULL_SYSTEM && (cpuXC->readPC() & 1)) ? PHYSICAL : 0,
+ cpuXC->readPC());
Fault fault = cpuXC->translateInstReq(req);
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index ed0c2da94..9cccb97f7 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -172,12 +172,10 @@ template <class T>
Fault
TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
{
- Request *data_read_req = new Request(true);
+ // need to fill in CPU & thread IDs here
+ Request *data_read_req = new Request();
- data_read_req->setVaddr(addr);
- data_read_req->setSize(sizeof(T));
- data_read_req->setFlags(flags);
- data_read_req->setTime(curTick);
+ data_read_req->setVirt(0, addr, sizeof(T), flags, cpuXC->readPC());
if (traceData) {
traceData->setAddr(data_read_req->getVaddr());
@@ -255,11 +253,9 @@ template <class T>
Fault
TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
{
- Request *data_write_req = new Request(true);
- data_write_req->setVaddr(addr);
- data_write_req->setTime(curTick);
- data_write_req->setSize(sizeof(T));
- data_write_req->setFlags(flags);
+ // need to fill in CPU & thread IDs here
+ Request *data_write_req = new Request();
+ data_write_req->setVirt(0, addr, sizeof(T), flags, cpuXC->readPC());
// translate to physical address
Fault fault = cpuXC->translateDataWriteReq(data_write_req);
@@ -340,8 +336,8 @@ TimingSimpleCPU::fetch()
{
checkForInterrupts();
- Request *ifetch_req = new Request(true);
- ifetch_req->setSize(sizeof(MachInst));
+ // need to fill in CPU & thread IDs here
+ Request *ifetch_req = new Request();
Fault fault = setupFetchRequest(ifetch_req);
ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);