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| author | Matt Horsnell <matt.horsnell@arm.com> | 2018-04-11 14:08:45 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-10-09 09:12:28 +0000 |
| commit | dd44f6bdff37fbd15a135da4d6a5b0fcf1ef2957 (patch) | |
| tree | 355253e906cdc565776c640824d2770ddacd44d4 /src/cpu | |
| parent | bb0ab1d464ff875b44cfce57e3c01c7587b02727 (diff) | |
| download | gem5-dd44f6bdff37fbd15a135da4d6a5b0fcf1ef2957.tar.xz | |
arch-arm: AArch32 Crypto SHA
This patch implements the AArch32 secure hashing instructions
from the Crypto extension.
Change-Id: Iaba8424ab71800228a9aff039d93f5c35ee7d8e5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13247
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/FuncUnit.py | 4 | ||||
| -rw-r--r-- | src/cpu/op_class.hh | 8 |
2 files changed, 10 insertions, 2 deletions
diff --git a/src/cpu/FuncUnit.py b/src/cpu/FuncUnit.py index d5983055d..e985a648a 100644 --- a/src/cpu/FuncUnit.py +++ b/src/cpu/FuncUnit.py @@ -1,4 +1,4 @@ -# Copyright (c) 2010 ARM Limited +# Copyright (c) 2010,2018 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -50,6 +50,8 @@ class OpClass(Enum): 'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu', 'SimdFloatCmp', 'SimdFloatCvt', 'SimdFloatDiv', 'SimdFloatMisc', 'SimdFloatMult', 'SimdFloatMultAcc', 'SimdFloatSqrt', + 'SimdSha1Hash', 'SimdSha1Hash2', 'SimdSha256Hash', + 'SimdSha256Hash2', 'SimdShaSigma2', 'SimdShaSigma3', 'MemRead', 'MemWrite', 'FloatMemRead', 'FloatMemWrite', 'IprAccess', 'InstPrefetch'] diff --git a/src/cpu/op_class.hh b/src/cpu/op_class.hh index adc7bae97..a4cadb96e 100644 --- a/src/cpu/op_class.hh +++ b/src/cpu/op_class.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010 ARM Limited + * Copyright (c) 2010,2018 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -83,6 +83,12 @@ static const OpClass SimdFloatMiscOp = Enums::SimdFloatMisc; static const OpClass SimdFloatMultOp = Enums::SimdFloatMult; static const OpClass SimdFloatMultAccOp = Enums::SimdFloatMultAcc; static const OpClass SimdFloatSqrtOp = Enums::SimdFloatSqrt; +static const OpClass SimdSha1HashOp = Enums::SimdSha1Hash; +static const OpClass SimdSha1Hash2Op = Enums::SimdSha1Hash2; +static const OpClass SimdSha256HashOp = Enums::SimdSha256Hash; +static const OpClass SimdSha256Hash2Op = Enums::SimdSha256Hash2; +static const OpClass SimdShaSigma2Op = Enums::SimdShaSigma2; +static const OpClass SimdShaSigma3Op = Enums::SimdShaSigma3; static const OpClass MemReadOp = Enums::MemRead; static const OpClass MemWriteOp = Enums::MemWrite; static const OpClass FloatMemReadOp = Enums::FloatMemRead; |