Merge zizzer.eecs.umich.edu:/bk/newmem/

into  zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops

--HG--
extra : convert_revision : dc165840841bdd88e40111b98d1be493441703f0

7 files changed, 160 insertions, 4 deletions

diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index 9d85311bb..80b144e85 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -33,6 +33,8 @@
 
 #include <fstream>
 #include <iomanip>
+#include <sys/ipc.h>
+#include <sys/shm.h>
 
 #include "arch/regfile.hh"
 #include "base/loader/symtab.hh"
@@ -44,10 +46,15 @@
 
 //XXX This is temporary
 #include "arch/isa_specific.hh"
+#include "cpu/m5legion_interface.h"
 
 using namespace std;
 using namespace TheISA;
 
+namespace Trace {
+SharedData *shared_data = NULL;
+}
+
 ////////////////////////////////////////////////////////////////////////
 //
 //  Methods for the InstRecord object
@@ -60,6 +67,7 @@ Trace::InstRecord::dump(ostream &outs)
     if (flags[PRINT_REG_DELTA])
     {
 #if THE_ISA == SPARC_ISA
+#if 0
         //Don't print what happens for each micro-op, just print out
         //once at the last op, and for regular instructions.
         if(!staticInst->isMicroOp() || staticInst->isLastMicroOp())
@@ -121,6 +129,7 @@ Trace::InstRecord::dump(ostream &outs)
             outs << endl;
         }
 #endif
+#endif
     }
     else if (flags[INTEL_FORMAT]) {
 #if FULL_SYSTEM
@@ -222,6 +231,65 @@ Trace::InstRecord::dump(ostream &outs)
         //
         outs << endl;
     }
+    // Compare
+    if (flags[LEGION_LOCKSTEP])
+    {
+        bool compared = false;
+        bool diffPC   = false;
+        bool diffInst = false;
+        bool diffRegs = false;
+
+        while (!compared) {
+            if (shared_data->flags == OWN_M5) {
+                if (shared_data->pc != PC)
+                   diffPC = true;
+                if (shared_data->instruction != staticInst->machInst)
+                    diffInst = true;
+                for (int i = 0; i < TheISA::NumIntRegs; i++) {
+                    if (thread->readIntReg(i) != shared_data->intregs[i])
+                        diffRegs = true;
+                }
+
+                if (diffPC || diffInst || diffRegs ) {
+                    outs << "Differences found between M5 and Legion:";
+                    if (diffPC)
+                        outs << " PC";
+                    if (diffInst)
+                        outs << " Instruction";
+                    if (diffRegs)
+                        outs << " IntRegs";
+                    outs << endl;
+
+                    outs << "M5 PC: " << setw(20) << "0x" << hex << PC;
+                    outs << "Legion PC: " << setw(20) << "0x" << hex <<
+                        shared_data->pc << endl;
+
+
+
+                    outs << "M5 Instruction: " << staticInst->machInst << "("
+                         << staticInst->disassemble(PC, debugSymbolTable)
+                         << ")" << "Legion Instruction: " <<
+                         shared_data->instruction << "("
+                         /*<< legionInst->disassemble(shared_data->pc,
+                                 debugSymbolTable)*/
+                         << ")" << endl;
+
+                    for (int i = 0; i < TheISA::NumIntRegs; i++) {
+                        outs << setw(16) << "0x" << hex << thread->readIntReg(i)
+                             << setw(16) << "0x" << hex << shared_data->intregs[i];
+
+                        if (thread->readIntReg(i) != shared_data->intregs[i])
+                            outs << "<--- Different";
+                        outs << endl;
+                    }
+                }
+
+                compared = true;
+                shared_data->flags = OWN_LEGION;
+            }
+        }
+
+    }
 }
 
 
@@ -271,6 +339,9 @@ Param<bool> exe_trace_pc_symbol(&exeTraceParams, "pc_symbol",
                                   "Use symbols for the PC if available", true);
 Param<bool> exe_trace_intel_format(&exeTraceParams, "intel_format",
                                    "print trace in intel compatible format", false);
+Param<bool> exe_trace_legion_lockstep(&exeTraceParams, "legion_lockstep",
+                                   "Compare sim state to legion state every cycle",
+                                   false);
 Param<string> exe_trace_system(&exeTraceParams, "trace_system",
                                    "print trace of which system (client or server)",
                                    "client");
@@ -296,7 +367,28 @@ Trace::InstRecord::setParams()
     flags[PRINT_REG_DELTA]   = exe_trace_print_reg_delta;
     flags[PC_SYMBOL]         = exe_trace_pc_symbol;
     flags[INTEL_FORMAT]      = exe_trace_intel_format;
+    flags[LEGION_LOCKSTEP]   = exe_trace_legion_lockstep;
     trace_system	     = exe_trace_system;
+
+    // If were going to be in lockstep with Legion
+    // Setup shared memory, and get otherwise ready
+    if (flags[LEGION_LOCKSTEP]) {
+        int shmfd = shmget(getuid(), sizeof(SharedData), 0777);
+        if (shmfd < 0)
+            fatal("Couldn't get shared memory fd. Is Legion running?");
+
+        shared_data = (SharedData*)shmat(shmfd, NULL, SHM_RND);
+        if (shared_data == (SharedData*)-1)
+            fatal("Couldn't allocate shared memory");
+
+        if (shared_data->flags != OWN_M5)
+            fatal("Shared memory has invalid owner");
+
+        if (shared_data->version != VERSION)
+            fatal("Shared Data is wrong version! M5: %d Legion: %d", VERSION,
+                    shared_data->version);
+
+    }
 }
 
 void
diff --git a/src/cpu/exetrace.hh b/src/cpu/exetrace.hh
index 02ea162f0..6562e5265 100644
--- a/src/cpu/exetrace.hh
+++ b/src/cpu/exetrace.hh
@@ -150,6 +150,7 @@ class InstRecord : public Record
         PRINT_REG_DELTA,
         PC_SYMBOL,
         INTEL_FORMAT,
+        LEGION_LOCKSTEP,
         NUM_BITS
     };
 
diff --git a/src/cpu/m5legion_interface.h b/src/cpu/m5legion_interface.h
new file mode 100644
index 000000000..0fa0e7279
--- /dev/null
+++ b/src/cpu/m5legion_interface.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+#include <unistd.h>
+
+#define VERSION         0xA1000001
+#define OWN_M5          0x000000AA
+#define OWN_LEGION      0x00000055
+
+/** !!!  VVV Increment VERSION on change VVV !!! **/
+
+typedef struct {
+    uint32_t flags;
+    uint32_t version;
+
+    uint64_t pc;
+    uint64_t instruction;
+    uint64_t intregs[32];
+
+} SharedData;
+
+/** !!! ^^^  Increment VERSION on change ^^^ !!! **/
+
diff --git a/src/cpu/o3/mem_dep_unit.hh b/src/cpu/o3/mem_dep_unit.hh
index e399f0133..a12a3001b 100644
--- a/src/cpu/o3/mem_dep_unit.hh
+++ b/src/cpu/o3/mem_dep_unit.hh
@@ -69,7 +69,7 @@ class MemDepUnit {
     typedef typename Impl::DynInstPtr DynInstPtr;
 
     /** Empty constructor. Must call init() prior to using in this case. */
-    MemDepUnit() {}
+    MemDepUnit();
 
     /** Constructs a MemDepUnit with given parameters. */
     MemDepUnit(Params *params);
diff --git a/src/cpu/o3/mem_dep_unit_impl.hh b/src/cpu/o3/mem_dep_unit_impl.hh
index c649ca385..f19980fd5 100644
--- a/src/cpu/o3/mem_dep_unit_impl.hh
+++ b/src/cpu/o3/mem_dep_unit_impl.hh
@@ -34,6 +34,13 @@
 #include "cpu/o3/mem_dep_unit.hh"
 
 template <class MemDepPred, class Impl>
+MemDepUnit<MemDepPred, Impl>::MemDepUnit()
+    : loadBarrier(false), loadBarrierSN(0), storeBarrier(false),
+      storeBarrierSN(0), iqPtr(NULL)
+{
+}
+
+template <class MemDepPred, class Impl>
 MemDepUnit<MemDepPred, Impl>::MemDepUnit(Params *params)
     : depPred(params->SSITSize, params->LFSTSize), loadBarrier(false),
       loadBarrierSN(0), storeBarrier(false), storeBarrierSN(0), iqPtr(NULL)
@@ -160,8 +167,12 @@ MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst)
     // producing memrefs/stores.
     InstSeqNum producing_store;
     if (inst->isLoad() && loadBarrier) {
+        DPRINTF(MemDepUnit, "Load barrier [sn:%lli] in flight\n",
+                loadBarrierSN);
         producing_store = loadBarrierSN;
     } else if (inst->isStore() && storeBarrier) {
+        DPRINTF(MemDepUnit, "Store barrier [sn:%lli] in flight\n",
+                storeBarrierSN);
         producing_store = storeBarrierSN;
     } else {
         producing_store = depPred.checkInst(inst->readPC());
@@ -171,10 +182,12 @@ MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst)
 
     // If there is a producing store, try to find the entry.
     if (producing_store != 0) {
+        DPRINTF(MemDepUnit, "Searching for producer\n");
         MemDepHashIt hash_it = memDepHash.find(producing_store);
 
         if (hash_it != memDepHash.end()) {
             store_entry = (*hash_it).second;
+            DPRINTF(MemDepUnit, "Proucer found\n");
         }
     }
 
diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index 2b2ed7b3e..c1373944d 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -361,8 +361,8 @@ class OzoneCPU : public BaseCPU
 
     bool interval_stats;
 
-    AlphaITB *itb;
-    AlphaDTB *dtb;
+    TheISA::ITB *itb;
+    TheISA::DTB *dtb;
     System *system;
     PhysicalMemory *physmem;
 #endif
diff --git a/src/cpu/ozone/thread_state.hh b/src/cpu/ozone/thread_state.hh
index c4d16b3af..a71795851 100644
--- a/src/cpu/ozone/thread_state.hh
+++ b/src/cpu/ozone/thread_state.hh
@@ -122,7 +122,7 @@ struct OzoneThreadState : public ThreadState {
 
     MiscReg readMiscRegWithEffect(int misc_reg)
     {
-        return miscRegFile.readRegWithEffect(misc_reg, fault, tc);
+        return miscRegFile.readRegWithEffect(misc_reg, tc);
     }
 
     void setMiscReg(int misc_reg, const MiscReg &val)