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authorGabe Black <gblack@eecs.umich.edu>2006-12-28 14:29:17 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-12-28 14:29:17 -0500
commit15df0a27bbf1409f974edbc1f5ffbdf2715ec4f9 (patch)
treec758ae05d5cbc17aaa557b143904313055acdd30 /src/cpu
parentb642ad00eb55678f4ce20fdf127a00a6c0bbdcb8 (diff)
downloadgem5-15df0a27bbf1409f974edbc1f5ffbdf2715ec4f9.tar.xz
Make sure the value of PC is actually updated now that the instruction target isn't set explicitly.
--HG-- extra : convert_revision : 4c00a219ac1d82abea78e4e8d70f529a435fdfe2
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/o3/bpred_unit_impl.hh4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/cpu/o3/bpred_unit_impl.hh b/src/cpu/o3/bpred_unit_impl.hh
index dbc603082..84c50b4da 100644
--- a/src/cpu/o3/bpred_unit_impl.hh
+++ b/src/cpu/o3/bpred_unit_impl.hh
@@ -149,7 +149,7 @@ BPredUnit<Impl>::predict(DynInstPtr &inst, Addr &PC, unsigned tid)
using TheISA::MachInst;
bool pred_taken = false;
- Addr target;
+ Addr target = PC;
++lookups;
@@ -233,6 +233,8 @@ BPredUnit<Impl>::predict(DynInstPtr &inst, Addr &PC, unsigned tid)
}
}
+ PC = target;
+
predHist[tid].push_front(predict_record);
DPRINTF(Fetch, "[tid:%i]: predHist.size(): %i\n", tid, predHist[tid].size());