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author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:21 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:21 -0700 |
commit | 1b29f1621d714c6dc0f2ab921f12e9eb1dbfcd46 (patch) | |
tree | 4e7adf45cefcd7364abf04b95cf9ab948e93df41 /src/cpu | |
parent | 0338c83c9d3db8ae71056c191bebc2df4ae9d513 (diff) | |
download | gem5-1b29f1621d714c6dc0f2ab921f12e9eb1dbfcd46.tar.xz |
ARM, Simple CPU: Fix an index and add assert checks.
Diffstat (limited to 'src/cpu')
-rw-r--r-- | src/cpu/simple_thread.hh | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index 97c02d7b8..35a28dbb6 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -242,36 +242,42 @@ class SimpleThread : public ThreadState uint64_t readIntReg(int reg_idx) { int flatIndex = isa.flattenIntIndex(reg_idx); + assert(flatIndex < TheISA::NumIntRegs); return intRegs[flatIndex]; } FloatReg readFloatReg(int reg_idx) { int flatIndex = isa.flattenFloatIndex(reg_idx); + assert(flatIndex < TheISA::NumFloatRegs); return floatRegs.f[flatIndex]; } FloatRegBits readFloatRegBits(int reg_idx) { int flatIndex = isa.flattenFloatIndex(reg_idx); + assert(flatIndex < TheISA::NumFloatRegs); return floatRegs.i[flatIndex]; } void setIntReg(int reg_idx, uint64_t val) { int flatIndex = isa.flattenIntIndex(reg_idx); + assert(flatIndex < TheISA::NumIntRegs); intRegs[flatIndex] = val; } void setFloatReg(int reg_idx, FloatReg val) { int flatIndex = isa.flattenFloatIndex(reg_idx); + assert(flatIndex < TheISA::NumFloatRegs); floatRegs.f[flatIndex] = val; } void setFloatRegBits(int reg_idx, FloatRegBits val) { int flatIndex = isa.flattenFloatIndex(reg_idx); + assert(flatIndex < TheISA::NumFloatRegs); floatRegs.i[flatIndex] = val; } |