cpu,arch-arm: Initialise data members

The value that is not initialized has a bogus value that manifests when
using some debug-flags what makes the usage of tracediff a bit more
challenging.

In addition, while debugging with other techniques, it introduces the
problem of understanding if the value of a field is 'intended' or just
an effect of the lack of initialisation.

Change-Id: Ied88caa77479c6f1d5166d80d1a1a057503cb106
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13125
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

10 files changed, 64 insertions, 15 deletions

diff --git a/src/cpu/base_dyn_inst_impl.hh b/src/cpu/base_dyn_inst_impl.hh
index f638f754c..cd4740de5 100644
--- a/src/cpu/base_dyn_inst_impl.hh
+++ b/src/cpu/base_dyn_inst_impl.hh
@@ -63,7 +63,15 @@ BaseDynInst<Impl>::BaseDynInst(const StaticInstPtr &_staticInst,
                                const StaticInstPtr &_macroop,
                                TheISA::PCState _pc, TheISA::PCState _predPC,
                                InstSeqNum seq_num, ImplCPU *cpu)
-  : staticInst(_staticInst), cpu(cpu), traceData(NULL), macroop(_macroop)
+  : staticInst(_staticInst), cpu(cpu),
+    thread(nullptr),
+    traceData(nullptr),
+    macroop(_macroop),
+    memData(nullptr),
+    savedReq(nullptr),
+    savedSreqLow(nullptr),
+    savedSreqHigh(nullptr),
+    reqToVerify(nullptr)
 {
     seqNum = seq_num;
 
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index 8329e3191..fe1c3d440 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -67,7 +67,9 @@ CheckerCPU::init()
 
 CheckerCPU::CheckerCPU(Params *p)
     : BaseCPU(p, true), systemPtr(NULL), icachePort(NULL), dcachePort(NULL),
-      tc(NULL), thread(NULL)
+      tc(NULL), thread(NULL),
+      unverifiedReq(nullptr),
+      unverifiedMemData(nullptr)
 {
     curStaticInst = NULL;
     curMacroStaticInst = NULL;
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 4775e98d1..40ce8480e 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -132,17 +132,19 @@ DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
                "RoundRobin, OldestReady");
     }
 
-    for (ThreadID tid = 0; tid < numThreads; tid++) {
+    for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
         commitStatus[tid] = Idle;
         changedROBNumEntries[tid] = false;
-        checkEmptyROB[tid] = false;
-        trapInFlight[tid] = false;
-        committedStores[tid] = false;
         trapSquash[tid] = false;
         tcSquash[tid] = false;
+        squashAfterInst[tid] = nullptr;
         pc[tid].set(0);
+        youngestSeqNum[tid] = 0;
         lastCommitedSeqNum[tid] = 0;
-        squashAfterInst[tid] = NULL;
+        trapInFlight[tid] = false;
+        committedStores[tid] = false;
+        checkEmptyROB[tid] = false;
+        renameMap[tid] = nullptr;
     }
     interrupt = NoFault;
 }
diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh
index 51c1b9de1..63b180ef9 100644
--- a/src/cpu/o3/decode_impl.hh
+++ b/src/cpu/o3/decode_impl.hh
@@ -75,6 +75,13 @@ DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params)
 
     // @todo: Make into a parameter
     skidBufferMax = (fetchToDecodeDelay + 1) *  params->fetchWidth;
+    for (int tid = 0; tid < Impl::MaxThreads; tid++) {
+        stalls[tid] = {false};
+        decodeStatus[tid] = Idle;
+        bdelayDoneSeqNum[tid] = 0;
+        squashInst[tid] = nullptr;
+        squashAfterDelaySlot[tid] = 0;
+    }
 }
 
 template<class Impl>
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index 28739d2dc..ce4f8b6b0 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -121,7 +121,7 @@ class DefaultFetch
 
       public:
         FinishTranslationEvent(DefaultFetch<Impl> *_fetch)
-            : fetch(_fetch)
+            : fetch(_fetch), req(nullptr)
         {}
 
         void setFault(Fault _fault)
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 5810c032f..537f93089 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -80,6 +80,7 @@ using namespace std;
 template<class Impl>
 DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params)
     : cpu(_cpu),
+      branchPred(nullptr),
       decodeToFetchDelay(params->decodeToFetchDelay),
       renameToFetchDelay(params->renameToFetchDelay),
       iewToFetchDelay(params->iewToFetchDelay),
@@ -143,10 +144,19 @@ DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params)
     instSize = sizeof(TheISA::MachInst);
 
     for (int i = 0; i < Impl::MaxThreads; i++) {
-        decoder[i] = NULL;
+        fetchStatus[i] = Idle;
+        decoder[i] = nullptr;
+        pc[i] = 0;
+        fetchOffset[i] = 0;
+        macroop[i] = nullptr;
+        delayedCommit[i] = false;
+        memReq[i] = nullptr;
+        stalls[i] = {false, false};
         fetchBuffer[i] = NULL;
         fetchBufferPC[i] = 0;
         fetchBufferValid[i] = false;
+        lastIcacheStall[i] = 0;
+        issuePipelinedIfetch[i] = false;
     }
 
     branchPred = params->branchPred;
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index e46bc5ba5..e706b09a1 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -76,6 +76,8 @@ DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params)
       issueToExecuteDelay(params->issueToExecuteDelay),
       dispatchWidth(params->dispatchWidth),
       issueWidth(params->issueWidth),
+      wbNumInst(0),
+      wbCycle(0),
       wbWidth(params->wbWidth),
       numThreads(params->numThreads)
 {
@@ -102,7 +104,7 @@ DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params)
     // Instruction queue needs the queue between issue and execute.
     instQueue.setIssueToExecuteQueue(&issueToExecQueue);
 
-    for (ThreadID tid = 0; tid < numThreads; tid++) {
+    for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
         dispatchStatus[tid] = Running;
         fetchRedirect[tid] = false;
     }
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index 410c15ffa..b34e6d980 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -113,7 +113,7 @@ InstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr,
     regScoreboard.resize(numPhysRegs);
 
     //Initialize Mem Dependence Units
-    for (ThreadID tid = 0; tid < numThreads; tid++) {
+    for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
         memDepUnit[tid].init(params, tid);
         memDepUnit[tid].setIQ(this);
     }
@@ -166,6 +166,9 @@ InstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr,
        panic("Invalid IQ sharing policy. Options are: Dynamic, "
               "Partitioned, Threshold");
    }
+    for (ThreadID tid = numThreads; tid < Impl::MaxThreads; tid++) {
+        maxEntries[tid] = 0;
+    }
 }
 
 template <class Impl>
@@ -407,7 +410,7 @@ void
 InstructionQueue<Impl>::resetState()
 {
     //Initialize thread IQ counts
-    for (ThreadID tid = 0; tid <numThreads; tid++) {
+    for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
         count[tid] = 0;
         instList[tid].clear();
     }
@@ -424,7 +427,7 @@ InstructionQueue<Impl>::resetState()
         regScoreboard[i] = false;
     }
 
-    for (ThreadID tid = 0; tid < numThreads; ++tid) {
+    for (ThreadID tid = 0; tid < Impl::MaxThreads; ++tid) {
         squashedSeqNum[tid] = 0;
     }
 
diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index a295a8705..4331b6d08 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -76,6 +76,18 @@ DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params)
 
     // @todo: Make into a parameter.
     skidBufferMax = (decodeToRenameDelay + 1) * params->decodeWidth;
+    for (uint32_t tid = 0; tid < Impl::MaxThreads; tid++) {
+        renameStatus[tid] = Idle;
+        renameMap[tid] = nullptr;
+        instsInProgress[tid] = 0;
+        loadsInProgress[tid] = 0;
+        storesInProgress[tid] = 0;
+        freeEntries[tid] = {0, 0, 0, 0};
+        emptyROB[tid] = true;
+        stalls[tid] = {false, false};
+        serializeInst[tid] = nullptr;
+        serializeOnNextInst[tid] = false;
+    }
 }
 
 template <class Impl>
diff --git a/src/cpu/o3/rob_impl.hh b/src/cpu/o3/rob_impl.hh
index 991dc967d..3a0140b9f 100644
--- a/src/cpu/o3/rob_impl.hh
+++ b/src/cpu/o3/rob_impl.hh
@@ -103,6 +103,9 @@ ROB<Impl>::ROB(O3CPU *_cpu, DerivO3CPUParams *params)
         panic("Invalid ROB sharing policy. Options are: Dynamic, "
                 "Partitioned, Threshold");
     }
+    for (ThreadID tid = numThreads; tid < Impl::MaxThreads; tid++) {
+        maxEntries[tid] = 0;
+    }
 
     resetState();
 }
@@ -111,11 +114,11 @@ template <class Impl>
 void
 ROB<Impl>::resetState()
 {
-    for (ThreadID tid = 0; tid  < numThreads; tid++) {
-        doneSquashing[tid] = true;
+    for (ThreadID tid = 0; tid  < Impl::MaxThreads; tid++) {
         threadEntries[tid] = 0;
         squashIt[tid] = instList[tid].end();
         squashedSeqNum[tid] = 0;
+        doneSquashing[tid] = true;
     }
     numInstsInROB = 0;