Merge vm1.(none):/home/stever/bk/newmem-head

into  vm1.(none):/home/stever/bk/newmem-cache2

--HG--
extra : convert_revision : a8efe71a50b9ae480c5ad0aabd7aa9ba22bc2968

3 files changed, 10 insertions, 12 deletions

diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 4dccee0d3..078ae1283 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -179,10 +179,9 @@ BaseCPU::BaseCPU(Params *p)
         if (p->functionTraceStart == 0) {
             functionTracingEnabled = true;
         } else {
-            Event *e =
-                new EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace>(this,
-                                                                         true);
-            e->schedule(p->functionTraceStart);
+            new EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace>(this,
+                                                                     p->functionTraceStart,
+                                                                     true);
         }
     }
 #if FULL_SYSTEM
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index fa7bb4f86..1c79fcf6b 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -168,9 +168,7 @@ TimingSimpleCPU::resume()
             delete fetchEvent;
         }
 
-        fetchEvent =
-            new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false);
-        fetchEvent->schedule(nextCycle());
+        fetchEvent = new FetchEvent(this, nextCycle());
     }
 
     changeState(SimObject::Running);
@@ -224,9 +222,7 @@ TimingSimpleCPU::activateContext(int thread_num, int delay)
     _status = Running;
 
     // kick things off by initiating the fetch of the next instruction
-    fetchEvent =
-        new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false);
-    fetchEvent->schedule(nextCycle(curTick + cycles(delay)));
+    fetchEvent = new FetchEvent(this, nextCycle(curTick + cycles(delay)));
 }
 
 
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index ef062d24a..e65cbe46b 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -66,8 +66,6 @@ class TimingSimpleCPU : public BaseSimpleCPU
 
     Event *drainEvent;
 
-    Event *fetchEvent;
-
   private:
 
     class CpuPort : public Port
@@ -199,7 +197,12 @@ class TimingSimpleCPU : public BaseSimpleCPU
     void completeIfetch(PacketPtr );
     void completeDataAccess(PacketPtr );
     void advanceInst(Fault fault);
+
   private:
+
+    typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;
+    FetchEvent *fetchEvent;
+
     void completeDrain();
 };