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author | Ali Saidi <saidi@eecs.umich.edu> | 2007-01-30 18:27:16 -0500 |
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committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-01-30 18:27:16 -0500 |
commit | 36a1912bf01433acc86837ed60da6d510323aa1e (patch) | |
tree | 7d9c35533d7e6a1c46cd75b98658bf6e46a55d48 /src/cpu | |
parent | cf0ba1dfb09c0e16201d963b76078625dc7adca4 (diff) | |
parent | ac36fb6e64dadb9eef5c48863b42969a61bbdaec (diff) | |
download | gem5-36a1912bf01433acc86837ed60da6d510323aa1e.tar.xz |
Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/work/m5.newmem
--HG--
extra : convert_revision : 276b640c5c5a51e88e9bd630960ad462d9f0cb8d
Diffstat (limited to 'src/cpu')
-rw-r--r-- | src/cpu/base.cc | 12 | ||||
-rw-r--r-- | src/cpu/base.hh | 6 | ||||
-rw-r--r-- | src/cpu/cpuevent.hh | 1 | ||||
-rw-r--r-- | src/cpu/exetrace.cc | 12 | ||||
-rw-r--r-- | src/cpu/m5legion_interface.h | 3 |
5 files changed, 31 insertions, 3 deletions
diff --git a/src/cpu/base.cc b/src/cpu/base.cc index deb4e02c4..8440d2320 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -298,6 +298,16 @@ BaseCPU::registerThreadContexts() } +int +BaseCPU::findContext(ThreadContext *tc) +{ + for (int i = 0; i < threadContexts.size(); ++i) { + if (tc == threadContexts[i]) + return i; + } + return 0; +} + void BaseCPU::switchOut() { @@ -389,12 +399,14 @@ BaseCPU::clear_interrupts() void BaseCPU::serialize(std::ostream &os) { + SERIALIZE_SCALAR(instCnt); interrupts.serialize(os); } void BaseCPU::unserialize(Checkpoint *cp, const std::string §ion) { + UNSERIALIZE_SCALAR(instCnt); interrupts.unserialize(cp, section); } diff --git a/src/cpu/base.hh b/src/cpu/base.hh index 3ae9c60b6..a1265b748 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -142,6 +142,12 @@ class BaseCPU : public MemObject /// Notify the CPU that the indicated context is now halted. virtual void haltContext(int thread_num) {} + /// Given a Thread Context pointer return the thread num + int findContext(ThreadContext *tc); + + /// Given a thread num get tho thread context for it + ThreadContext *getContext(int tn) { return threadContexts[tn]; } + public: struct Params { diff --git a/src/cpu/cpuevent.hh b/src/cpu/cpuevent.hh index c973621c0..5816c6ca1 100644 --- a/src/cpu/cpuevent.hh +++ b/src/cpu/cpuevent.hh @@ -71,6 +71,7 @@ class CpuEvent : public Event */ static void replaceThreadContext(ThreadContext *oldTc, ThreadContext *newTc); + ThreadContext* getTC() { return tc; } }; template <class T, void (T::* F)(ThreadContext *tc)> diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc index 85b08ee32..e34ae3731 100644 --- a/src/cpu/exetrace.cc +++ b/src/cpu/exetrace.cc @@ -307,6 +307,7 @@ Trace::InstRecord::dump(ostream &outs) bool diffHtba = false; bool diffPstate = false; bool diffY = false; + bool diffFsr = false; bool diffCcr = false; bool diffTl = false; bool diffGl = false; @@ -410,6 +411,8 @@ Trace::InstRecord::dump(ostream &outs) if(shared_data->y != thread->readIntReg(NumIntArchRegs + 1)) diffY = true; + if(shared_data->fsr != thread->readMiscReg(MISCREG_FSR)) + diffFsr = true; //if(shared_data->ccr != thread->readMiscReg(MISCREG_CCR)) if(shared_data->ccr != thread->readIntReg(NumIntArchRegs + 2)) @@ -450,8 +453,8 @@ Trace::InstRecord::dump(ostream &outs) if ((diffPC || diffCC || diffInst || diffIntRegs || diffFpRegs || diffTpc || diffTnpc || diffTstate || diffTt || diffHpstate || diffHtstate || diffHtba || - diffPstate || diffY || diffCcr || diffTl || diffGl || - diffAsi || diffPil || diffCwp || diffCansave || + diffPstate || diffY || diffCcr || diffTl || diffFsr || + diffGl || diffAsi || diffPil || diffCwp || diffCansave || diffCanrestore || diffOtherwin || diffCleanwin || diffTlb) && !((staticInst->machInst & 0xC1F80000) == 0x81D00000) && !(((staticInst->machInst & 0xC0000000) == 0xC0000000) @@ -487,6 +490,8 @@ Trace::InstRecord::dump(ostream &outs) outs << " [Pstate]"; if (diffY) outs << " [Y]"; + if (diffFsr) + outs << " [FSR]"; if (diffCcr) outs << " [Ccr]"; if (diffTl) @@ -556,6 +561,9 @@ Trace::InstRecord::dump(ostream &outs) //thread->readMiscReg(MISCREG_Y), thread->readIntReg(NumIntArchRegs + 1), shared_data->y); + printRegPair(outs, "FSR", + thread->readMiscReg(MISCREG_FSR), + shared_data->fsr); printRegPair(outs, "Ccr", //thread->readMiscReg(MISCREG_CCR), thread->readIntReg(NumIntArchRegs + 2), diff --git a/src/cpu/m5legion_interface.h b/src/cpu/m5legion_interface.h index 81714f769..373dc5cdc 100644 --- a/src/cpu/m5legion_interface.h +++ b/src/cpu/m5legion_interface.h @@ -30,7 +30,7 @@ #include <unistd.h> -#define VERSION 0xA1000008 +#define VERSION 0xA1000009 #define OWN_M5 0x000000AA #define OWN_LEGION 0x00000055 @@ -61,6 +61,7 @@ typedef struct { uint16_t pstate; uint64_t y; + uint64_t fsr; uint8_t ccr; uint8_t tl; uint8_t gl; |