Fix some unset values in the request in the timing CPU.

Properly implement the MSHR allocate function.

src/cpu/simple/timing.cc:
    Set the thread context in the CPU.

    Need to do this properly, currently I just set it to Cpu=0 Thread=0.  This will just cause all the stats in the cache based on these to just yield totals and not a distribution.
src/mem/cache/miss/mshr.cc:
    Properly implement the allocate function for the MSHR.

--HG--
extra : convert_revision : bcece518e54ed1404db3196f996a77b4dd5c1c1e

1 files changed, 3 insertions, 1 deletions

diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 0729f9489..d5bdcfa9b 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -207,7 +207,7 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
 {
     // need to fill in CPU & thread IDs here
     Request *data_read_req = new Request();
-
+    data_read_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
     data_read_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
 
     if (traceData) {
@@ -288,6 +288,7 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
 {
     // need to fill in CPU & thread IDs here
     Request *data_write_req = new Request();
+    data_write_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
     data_write_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
 
     // translate to physical address
@@ -371,6 +372,7 @@ TimingSimpleCPU::fetch()
 
     // need to fill in CPU & thread IDs here
     Request *ifetch_req = new Request();
+    ifetch_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
     Fault fault = setupFetchRequest(ifetch_req);
 
     ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);