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| author | Gabe Black <gblack@eecs.umich.edu> | 2006-12-18 18:20:13 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-12-18 18:20:13 -0500 |
| commit | 5b41ab694c9f1f2ae7183da48704eba34fc049ab (patch) | |
| tree | b6b87a970518484e894f0986e7970550d3bcb097 /src/cpu | |
| parent | dfafe6741f9865a996488236421d57ea1e6ba815 (diff) | |
| download | gem5-5b41ab694c9f1f2ae7183da48704eba34fc049ab.tar.xz | |
Fix a place where the wrong width parameter was used, and set the nextNPC correctly on memory squashes.
--HG--
extra : convert_revision : 7914a48ea953607c48f93984e3b043098f0d7c62
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/o3/iew_impl.hh | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh index 70200d648..787d8a26c 100644 --- a/src/cpu/o3/iew_impl.hh +++ b/src/cpu/o3/iew_impl.hh @@ -546,7 +546,7 @@ DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid) toCommit->squashedSeqNum[tid] = inst->seqNum; toCommit->nextPC[tid] = inst->readPC(); #if ISA_HAS_DELAY_SLOT - toCommit->nextNPC[tid] = inst->readNextNPC(); + toCommit->nextNPC[tid] = inst->readNextPC(); #endif toCommit->branchMispredict[tid] = false; @@ -1436,7 +1436,7 @@ DefaultIEW<Impl>::writebackInsts() // mark scoreboard that this instruction is finally complete. // Either have IEW have direct access to scoreboard, or have this // as part of backwards communication. - for (int inst_num = 0; inst_num < issueWidth && + for (int inst_num = 0; inst_num < wbWidth && toCommit->insts[inst_num]; inst_num++) { DynInstPtr inst = toCommit->insts[inst_num]; int tid = inst->threadNumber; |