Merge zizzer:/bk/newmem

into  zed.eecs.umich.edu:/z/hsul/work/sparc/x86.m5

--HG--
extra : convert_revision : 1b854ec7caa33d3009383754206b643494c4c42d

8 files changed, 4 insertions, 22 deletions

diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index b03bc19a5..deb4e02c4 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -96,7 +96,7 @@ CPUProgressEvent::description()
 
 #if FULL_SYSTEM
 BaseCPU::BaseCPU(Params *p)
-    : MemObject(p->name), clock(p->clock), instCnt(0), checkInterrupts(true),
+    : MemObject(p->name), clock(p->clock), instCnt(0),
       params(p), number_of_threads(p->numberOfThreads), system(p->system),
       phase(p->phase)
 #else
@@ -334,7 +334,6 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
 
 #if FULL_SYSTEM
     interrupts = oldCPU->interrupts;
-    checkInterrupts = oldCPU->checkInterrupts;
 
     for (int i = 0; i < threadContexts.size(); ++i)
         threadContexts[i]->profileClear();
@@ -371,7 +370,6 @@ BaseCPU::post_interrupt(int int_type)
 void
 BaseCPU::post_interrupt(int int_num, int index)
 {
-    checkInterrupts = true;
     interrupts.post(int_num, index);
 }
 
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 89c7d9dda..3ae9c60b6 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -106,7 +106,6 @@ class BaseCPU : public MemObject
     virtual void post_interrupt(int int_num, int index);
     virtual void clear_interrupt(int int_num, int index);
     virtual void clear_interrupts();
-    bool checkInterrupts;
 
     bool check_interrupts(ThreadContext * tc) const
     { return interrupts.check_interrupts(tc); }
diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh
index 98fd0699a..980e70fdd 100644
--- a/src/cpu/o3/alpha/cpu_impl.hh
+++ b/src/cpu/o3/alpha/cpu_impl.hh
@@ -217,8 +217,6 @@ AlphaO3CPU<Impl>::hwrei(unsigned tid)
 
     this->thread[tid]->kernelStats->hwrei();
 
-    this->checkInterrupts = true;
-
     // FIXME: XXX check for interrupts? XXX
     return NoFault;
 }
@@ -270,7 +268,6 @@ AlphaO3CPU<Impl>::processInterrupts(Fault interrupt)
     this->interrupts.updateIntrInfo(this->threadContexts[0]);
 
     DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
-    this->checkInterrupts = false;
     this->trap(interrupt, 0);
 }
 
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 96f094926..483c2f71b 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -671,8 +671,7 @@ DefaultCommit<Impl>::commit()
         } else {
             DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
         }
-    } else if (cpu->checkInterrupts &&
-        cpu->check_interrupts(cpu->tcBase(0)) &&
+    } else if (cpu->check_interrupts(cpu->tcBase(0)) &&
         commitStatus[0] != TrapPending &&
         !trapSquash[0] &&
         !tcSquash[0]) {
diff --git a/src/cpu/o3/sparc/cpu_impl.hh b/src/cpu/o3/sparc/cpu_impl.hh
index 536a620bf..66bf7d1c0 100644
--- a/src/cpu/o3/sparc/cpu_impl.hh
+++ b/src/cpu/o3/sparc/cpu_impl.hh
@@ -245,7 +245,6 @@ SparcO3CPU<Impl>::processInterrupts(Fault interrupt)
     this->interrupts.updateIntrInfo(this->threadContexts[0]);
 
     DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
-    this->checkInterrupts = false;
     this->trap(interrupt, 0);
 }
 
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index accc8d294..a854de8de 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -182,10 +182,6 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
 
     globalSeqNum = 1;
 
-#if FULL_SYSTEM
-    checkInterrupts = false;
-#endif
-
     lockFlag = 0;
 
     // Setup rename table, initializing all values to ready.
@@ -684,8 +680,6 @@ OzoneCPU<Impl>::hwrei()
     lockAddrList.clear();
     thread.kernelStats->hwrei();
 
-    checkInterrupts = true;
-
     // FIXME: XXX check for interrupts? XXX
     return NoFault;
 }
@@ -704,7 +698,6 @@ OzoneCPU<Impl>::processInterrupts()
 
     if (interrupt != NoFault) {
         this->interrupts.updateIntrInfo(thread.getTC());
-        this->checkInterrupts = false;
         interrupt->invoke(thread.getTC());
     }
 }
diff --git a/src/cpu/ozone/inorder_back_end_impl.hh b/src/cpu/ozone/inorder_back_end_impl.hh
index 87bf0a7a2..84f935a72 100644
--- a/src/cpu/ozone/inorder_back_end_impl.hh
+++ b/src/cpu/ozone/inorder_back_end_impl.hh
@@ -88,7 +88,6 @@ InorderBackEnd<Impl>::checkInterrupts()
     int ipl = 0;
     int summary = 0;
 
-    cpu->checkInterrupts = false;
 
     if (thread->readMiscReg(IPR_ASTRR))
         panic("asynchronous traps not implemented\n");
@@ -151,8 +150,7 @@ InorderBackEnd<Impl>::tick()
     // I'm waiting for it to drain.  (for now just squash)
 #if FULL_SYSTEM
     if (interruptBlocked ||
-        (cpu->checkInterrupts &&
-        cpu->check_interrupts(tc))) {
+        cpu->check_interrupts(tc)) {
         if (!robEmpty()) {
             interruptBlocked = true;
         //AlphaDep
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 14fefe103..b8d1f3bed 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -311,12 +311,11 @@ void
 BaseSimpleCPU::checkForInterrupts()
 {
 #if FULL_SYSTEM
-    if (checkInterrupts && check_interrupts(tc)) {
+    if (check_interrupts(tc)) {
         Fault interrupt = interrupts.getInterrupt(tc);
 
         if (interrupt != NoFault) {
             interrupts.updateIntrInfo(tc);
-            checkInterrupts = false;
             interrupt->invoke(tc);
         }
     }