SE/FS: Get rid of FULL_SYSTEM in the CPU directory.

56 files changed, 492 insertions, 781 deletions

diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 1ff4c85b4..b5c203742 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -81,8 +81,7 @@ class BaseCPU(MemObject):
     profile = Param.Latency('0ns', "trace the kernel stack")
     do_quiesce = Param.Bool(True, "enable quiesce instructions")
 
-    if not buildEnv['FULL_SYSTEM']:
-        workload = VectorParam.Process("processes to run")
+    workload = VectorParam.Process([], "processes to run")
 
     if buildEnv['TARGET_ISA'] == 'sparc':
         dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index c6743caa0..ff731336a 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -129,10 +129,9 @@ Source('simple_thread.cc')
 Source('thread_context.cc')
 Source('thread_state.cc')
 
-if env['FULL_SYSTEM']:
-    if env['TARGET_ISA'] == 'sparc':
-        SimObject('LegionTrace.py')
-        Source('legiontrace.cc')
+if env['TARGET_ISA'] == 'sparc':
+    SimObject('LegionTrace.py')
+    Source('legiontrace.cc')
 
 if env['USE_CHECKER']:
     Source('checker/cpu.cc')
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index f20618698..8a755a4bf 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -199,11 +199,9 @@ BaseCPU::BaseCPU(Params *p)
     interrupts->setCPU(this);
 
     if (FullSystem) {
-#if FULL_SYSTEM
         profileEvent = NULL;
         if (params()->profile)
             profileEvent = new ProfileEvent(this, params()->profile);
-#endif
     }
     tracer = params()->tracer;
 }
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index c15186e84..46d926808 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -158,7 +158,7 @@ class BaseCPU : public MemObject
     bool
     checkInterrupts(ThreadContext *tc) const
     {
-        return interrupts->checkInterrupts(tc);
+        return FullSystem && interrupts->checkInterrupts(tc);
     }
 
     class ProfileEvent : public Event
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index 0c7fe66bf..ec4496eb4 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -31,17 +31,14 @@
 #include <list>
 #include <string>
 
+#include "arch/kernel_stats.hh"
+#include "arch/vtophys.hh"
 #include "cpu/checker/cpu.hh"
 #include "cpu/base.hh"
 #include "cpu/simple_thread.hh"
 #include "cpu/static_inst.hh"
 #include "cpu/thread_context.hh"
 
-#if FULL_SYSTEM
-#include "arch/kernel_stats.hh"
-#include "arch/vtophys.hh"
-#endif // FULL_SYSTEM
-
 using namespace std;
 //The CheckerCPU does alpha only
 using namespace AlphaISA;
@@ -66,17 +63,14 @@ CheckerCPU::CheckerCPU(Params *p)
 
     exitOnError = p->exitOnError;
     warnOnlyOnLoadError = p->warnOnlyOnLoadError;
-#if FULL_SYSTEM
     itb = p->itb;
     dtb = p->dtb;
     systemPtr = NULL;
-#else
     process = p->process;
     thread = new SimpleThread(this, /* thread_num */ 0, process);
 
     tc = thread->getTC();
     threadContexts.push_back(tc);
-#endif
 
     result.integer = 0;
 }
@@ -88,7 +82,6 @@ CheckerCPU::~CheckerCPU()
 void
 CheckerCPU::setSystem(System *system)
 {
-#if FULL_SYSTEM
     systemPtr = system;
 
     thread = new SimpleThread(this, 0, systemPtr, itb, dtb, false);
@@ -97,7 +90,6 @@ CheckerCPU::setSystem(System *system)
     threadContexts.push_back(tc);
     delete thread->kernelStats;
     thread->kernelStats = NULL;
-#endif
 }
 
 void
@@ -301,13 +293,11 @@ CheckerCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
 }
 
 
-#if FULL_SYSTEM
 Addr
 CheckerCPU::dbg_vtophys(Addr addr)
 {
     return vtophys(tc, addr);
 }
-#endif // FULL_SYSTEM
 
 bool
 CheckerCPU::checkFlags(Request *req)
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 1e3a17a34..882575f89 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -46,25 +46,20 @@
 #include "sim/eventq.hh"
 
 // forward declarations
-#if FULL_SYSTEM
 namespace TheISA
 {
     class TLB;
 }
-class Processor;
-class PhysicalMemory;
-
-#else
 
-class Process;
-
-#endif // FULL_SYSTEM
 template <class>
 class BaseDynInst;
 class CheckerCPUParams;
-class ThreadContext;
-class MemInterface;
 class Checkpoint;
+class MemInterface;
+class PhysicalMemory;
+class Process;
+class Processor;
+class ThreadContext;
 class Request;
 
 /**
@@ -129,9 +124,7 @@ class CheckerCPU : public BaseCPU
     TheISA::TLB *itb;
     TheISA::TLB *dtb;
 
-#if FULL_SYSTEM
     Addr dbg_vtophys(Addr addr);
-#endif
 
     union Result {
         uint64_t integer;
@@ -273,14 +266,11 @@ class CheckerCPU : public BaseCPU
         this->dtb->demapPage(vaddr, asn);
     }
 
-#if FULL_SYSTEM
     Fault hwrei() { return thread->hwrei(); }
     bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
-#else
     // Assume that the normal CPU's call to syscall was successful.
     // The checker's state would have already been updated by the syscall.
     void syscall(uint64_t callnum) { }
-#endif
 
     void handleError()
     {
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 8694dae21..7d8cc8a19 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -31,6 +31,7 @@
 #include <list>
 #include <string>
 
+#include "arch/vtophys.hh"
 #include "base/refcnt.hh"
 #include "config/the_isa.hh"
 #include "cpu/checker/cpu.hh"
@@ -38,13 +39,10 @@
 #include "cpu/simple_thread.hh"
 #include "cpu/static_inst.hh"
 #include "cpu/thread_context.hh"
+#include "sim/full_system.hh"
 #include "sim/sim_object.hh"
 #include "sim/stats.hh"
 
-#if FULL_SYSTEM
-#include "arch/vtophys.hh"
-#endif // FULL_SYSTEM
-
 using namespace std;
 //The CheckerCPU does alpha only
 using namespace AlphaISA;
@@ -141,11 +139,7 @@ Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
 
         // Try to fetch the instruction
 
-#if FULL_SYSTEM
-#define IFETCH_FLAGS(pc)        ((pc) & 1) ? PHYSICAL : 0
-#else
-#define IFETCH_FLAGS(pc)        0
-#endif
+#define IFETCH_FLAGS(pc) (FullSystem ? 0 : ((pc) & 1) ? PHYSICAL : 0)
 
         uint64_t fetch_PC = thread->readPC() & ~3;
 
@@ -235,12 +229,10 @@ Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
         }
 
         if (fault != NoFault) {
-#if FULL_SYSTEM
             fault->invoke(tc, curStaticInst);
             willChangePC = true;
             newPC = thread->readPC();
             DPRINTF(Checker, "Fault, PC is now %#x\n", newPC);
-#endif
         } else {
 #if THE_ISA != MIPS_ISA
             // go to the next instruction
@@ -255,23 +247,23 @@ Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
 
         }
 
-#if FULL_SYSTEM
-        // @todo: Determine if these should happen only if the
-        // instruction hasn't faulted.  In the SimpleCPU case this may
-        // not be true, but in the O3 or Ozone case this may be true.
-        Addr oldpc;
-        int count = 0;
-        do {
-            oldpc = thread->readPC();
-            system->pcEventQueue.service(tc);
-            count++;
-        } while (oldpc != thread->readPC());
-        if (count > 1) {
-            willChangePC = true;
-            newPC = thread->readPC();
-            DPRINTF(Checker, "PC Event, PC is now %#x\n", newPC);
+        if (FullSystem) {
+            // @todo: Determine if these should happen only if the
+            // instruction hasn't faulted.  In the SimpleCPU case this may
+            // not be true, but in the O3 or Ozone case this may be true.
+            Addr oldpc;
+            int count = 0;
+            do {
+                oldpc = thread->readPC();
+                system->pcEventQueue.service(tc);
+                count++;
+            } while (oldpc != thread->readPC());
+            if (count > 1) {
+                willChangePC = true;
+                newPC = thread->readPC();
+                DPRINTF(Checker, "PC Event, PC is now %#x\n", newPC);
+            }
         }
-#endif
 
         // @todo:  Optionally can check all registers. (Or just those
         // that have been modified).
diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index 8b741080b..6c3c50a9c 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -89,14 +89,13 @@ class CheckerThreadContext : public ThreadContext
 
     TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
 
-#if FULL_SYSTEM
     System *getSystemPtr() { return actualTC->getSystemPtr(); }
 
     PhysicalMemory *getPhysMemPtr() { return actualTC->getPhysMemPtr(); }
 
     TheISA::Kernel::Statistics *getKernelStats()
     { return actualTC->getKernelStats(); }
-#endif
+
     Process *getProcessPtr() { return actualTC->getProcessPtr(); }
 
     TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
@@ -124,9 +123,7 @@ class CheckerThreadContext : public ThreadContext
     /// Set the status to Halted.
     void halt() { actualTC->halt(); }
 
-#if FULL_SYSTEM
     void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
-#endif
 
     void takeOverFrom(ThreadContext *oldContext)
     {
@@ -140,7 +137,6 @@ class CheckerThreadContext : public ThreadContext
     void unserialize(Checkpoint *cp, const std::string &section)
     { actualTC->unserialize(cp, section); }
 
-#if FULL_SYSTEM
     EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
 
     Tick readLastActivate() { return actualTC->readLastActivate(); }
@@ -148,7 +144,6 @@ class CheckerThreadContext : public ThreadContext
 
     void profileClear() { return actualTC->profileClear(); }
     void profileSample() { return actualTC->profileSample(); }
-#endif
 
     int threadId() { return actualTC->threadId(); }
 
@@ -252,9 +247,7 @@ class CheckerThreadContext : public ThreadContext
     // @todo: Fix this!
     bool misspeculating() { return actualTC->misspeculating(); }
 
-#if !FULL_SYSTEM
     Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
-#endif
 };
 
 #endif // __CPU_CHECKER_EXEC_CONTEXT_HH__
diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index 40991652d..0b21a1270 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -83,10 +83,7 @@ Trace::ExeTracerRecord::traceInst(StaticInstPtr inst, bool ran)
     std::string sym_str;
     Addr sym_addr;
     Addr cur_pc = pc.instAddr();
-    if (debugSymbolTable && Debug::ExecSymbol
-#if FULL_SYSTEM
-        && !inUserMode(thread)
-#endif
+    if (debugSymbolTable && Debug::ExecSymbol && !inUserMode(thread)
         && debugSymbolTable->findNearestSymbol(cur_pc, sym_str, sym_addr)) {
         if (cur_pc != sym_addr)
             sym_str += csprintf("+%d",cur_pc - sym_addr);
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 226b2d8ea..9d6ecc7e1 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -33,7 +33,6 @@
 
 #include "arch/utility.hh"
 #include "base/bigint.hh"
-#include "config/full_system.hh"
 #include "config/the_isa.hh"
 #include "cpu/inorder/resources/resource_list.hh"
 #include "cpu/inorder/cpu.hh"
@@ -51,11 +50,13 @@
 #include "cpu/thread_context.hh"
 #include "debug/Activity.hh"
 #include "debug/InOrderCPU.hh"
+#include "debug/Interrupt.hh"
 #include "debug/RefCount.hh"
 #include "debug/SkedCache.hh"
 #include "debug/Quiesce.hh"
 #include "mem/translating_port.hh"
 #include "params/InOrderCPU.hh"
+#include "sim/full_system.hh"
 #include "sim/process.hh"
 #include "sim/stat_control.hh"
 #include "sim/system.hh"
@@ -150,12 +151,11 @@ InOrderCPU::CPUEvent::process()
         cpu->trapPending[tid] = false;
         break;
 
-#if !FULL_SYSTEM
       case Syscall:
         cpu->syscall(inst->syscallNum, tid);
         cpu->resPool->trap(fault, tid, inst);
         break;
-#endif
+
       default:
         fatal("Unrecognized Event Type %s", eventNames[cpuEventType]);    
     }
@@ -195,9 +195,7 @@ InOrderCPU::InOrderCPU(Params *params)
       timeBuffer(2 , 2),
       removeInstsThisCycle(false),
       activityRec(params->name, NumStages, 10, params->activity),
-#if FULL_SYSTEM
       system(params->system),
-#endif // FULL_SYSTEM
 #ifdef DEBUG
       cpuEventNum(0),
       resReqCount(0),
@@ -216,35 +214,32 @@ InOrderCPU::InOrderCPU(Params *params)
     // Resize for Multithreading CPUs
     thread.resize(numThreads);
 
-#if FULL_SYSTEM
-    active_threads = 1;
-#else
-    active_threads = params->workload.size();
+    if (FullSystem) {
+        active_threads = 1;
+    } else {
+        active_threads = params->workload.size();
 
-    if (active_threads > MaxThreads) {
-        panic("Workload Size too large. Increase the 'MaxThreads'"
-              "in your InOrder implementation or "
-              "edit your workload size.");
-    }
+        if (active_threads > MaxThreads) {
+            panic("Workload Size too large. Increase the 'MaxThreads'"
+                  "in your InOrder implementation or "
+                  "edit your workload size.");
+        }
 
-    
-    if (active_threads > 1) {
-        threadModel = (InOrderCPU::ThreadModel) params->threadModel;
-
-        if (threadModel == SMT) {
-            DPRINTF(InOrderCPU, "Setting Thread Model to SMT.\n");            
-        } else if (threadModel == SwitchOnCacheMiss) {
-            DPRINTF(InOrderCPU, "Setting Thread Model to "
-                    "Switch On Cache Miss\n");
+
+        if (active_threads > 1) {
+            threadModel = (InOrderCPU::ThreadModel) params->threadModel;
+
+            if (threadModel == SMT) {
+                DPRINTF(InOrderCPU, "Setting Thread Model to SMT.\n");
+            } else if (threadModel == SwitchOnCacheMiss) {
+                DPRINTF(InOrderCPU, "Setting Thread Model to "
+                        "Switch On Cache Miss\n");
+            }
+
+        } else {
+            threadModel = Single;
         }
-        
-    } else {
-        threadModel = Single;
     }
-     
-        
-    
-#endif
 
     // Bind the fetch & data ports from the resource pool.
     fetchPortIdx = resPool->getPortIdx(params->fetchMemPort);
@@ -261,36 +256,34 @@ InOrderCPU::InOrderCPU(Params *params)
         pc[tid].set(0);
         lastCommittedPC[tid].set(0);
 
-#if FULL_SYSTEM
-        // SMT is not supported in FS mode yet.
-        assert(numThreads == 1);
-        thread[tid] = new Thread(this, 0, NULL);
-#else
-        if (tid < (ThreadID)params->workload.size()) {
-            DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n",
-                    tid, params->workload[tid]->prog_fname);
-            thread[tid] =
-                new Thread(this, tid, params->workload[tid]);
+        if (FullSystem) {
+            // SMT is not supported in FS mode yet.
+            assert(numThreads == 1);
+            thread[tid] = new Thread(this, 0, NULL);
         } else {
-            //Allocate Empty thread so M5 can use later
-            //when scheduling threads to CPU
-            Process* dummy_proc = params->workload[0];
-            thread[tid] = new Thread(this, tid, dummy_proc);
+            if (tid < (ThreadID)params->workload.size()) {
+                DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n",
+                        tid, params->workload[tid]->prog_fname);
+                thread[tid] =
+                    new Thread(this, tid, params->workload[tid]);
+            } else {
+                //Allocate Empty thread so M5 can use later
+                //when scheduling threads to CPU
+                Process* dummy_proc = params->workload[0];
+                thread[tid] = new Thread(this, tid, dummy_proc);
+            }
+
+            // Eventually set this with parameters...
+            asid[tid] = tid;
         }
-        
-        // Eventually set this with parameters...
-        asid[tid] = tid;
-#endif
 
         // Setup the TC that will serve as the interface to the threads/CPU.
         InOrderThreadContext *tc = new InOrderThreadContext;
         tc->cpu = this;
         tc->thread = thread[tid];
 
-#if FULL_SYSTEM
         // Setup quiesce event.
         this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
-#endif
 
         // Give the thread the TC.
         thread[tid]->tc = tc;
@@ -349,16 +342,17 @@ InOrderCPU::InOrderCPU(Params *params)
 
         dummyReq[tid] = new ResourceRequest(resPool->getResource(0));
 
-#if FULL_SYSTEM
-    // Use this dummy inst to force squashing behind every instruction
-    // in pipeline
-    dummyTrapInst[tid] = new InOrderDynInst(this, NULL, 0, 0, 0);
-    dummyTrapInst[tid]->seqNum = 0;
-    dummyTrapInst[tid]->squashSeqNum = 0;
-    dummyTrapInst[tid]->setTid(tid);
-#endif
 
-    trapPending[tid] = false;
+        if (FullSystem) {
+            // Use this dummy inst to force squashing behind every instruction
+            // in pipeline
+            dummyTrapInst[tid] = new InOrderDynInst(this, NULL, 0, 0, 0);
+            dummyTrapInst[tid]->seqNum = 0;
+            dummyTrapInst[tid]->squashSeqNum = 0;
+            dummyTrapInst[tid]->setTid(tid);
+        }
+
+        trapPending[tid] = false;
 
     }
 
@@ -699,9 +693,7 @@ InOrderCPU::tick()
 
     ++numCycles;
 
-#if FULL_SYSTEM
     checkForInterrupts();
-#endif
 
     bool pipes_idle = true;
     //Tick each of the stages
@@ -762,12 +754,12 @@ InOrderCPU::init()
     for (ThreadID tid = 0; tid < numThreads; ++tid)
         thread[tid]->inSyscall = true;
 
-#if FULL_SYSTEM
-    for (ThreadID tid = 0; tid < numThreads; tid++) {
-        ThreadContext *src_tc = threadContexts[tid];
-        TheISA::initCPU(src_tc, src_tc->contextId());
+    if (FullSystem) {
+        for (ThreadID tid = 0; tid < numThreads; tid++) {
+            ThreadContext *src_tc = threadContexts[tid];
+            TheISA::initCPU(src_tc, src_tc->contextId());
+        }
     }
-#endif
 
     // Clear inSyscall.
     for (ThreadID tid = 0; tid < numThreads; ++tid)
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index 8e915c08c..dc5a23b98 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -780,10 +780,8 @@ class InOrderCPU : public BaseCPU
         return total;
     }
 
-#if FULL_SYSTEM
     /** Pointer to the system. */
     System *system;
-#endif
 
     /** The global sequence number counter. */
     InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
diff --git a/src/cpu/inorder/inorder_cpu_builder.cc b/src/cpu/inorder/inorder_cpu_builder.cc
index 99729577e..bde5b1e94 100644
--- a/src/cpu/inorder/inorder_cpu_builder.cc
+++ b/src/cpu/inorder/inorder_cpu_builder.cc
@@ -38,21 +38,23 @@
 #include "cpu/inst_seq.hh"
 #include "cpu/static_inst.hh"
 #include "params/InOrderCPU.hh"
+#include "sim/full_system.hh"
 
 InOrderCPU *
 InOrderCPUParams::create()
 {
-#if FULL_SYSTEM
-    // Full-system only supports a single thread for the moment.
-    ThreadID actual_num_threads = 1;
-#else
-    ThreadID actual_num_threads =
-        (numThreads >= workload.size()) ? numThreads : workload.size();
+    ThreadID actual_num_threads;
+    if (FullSystem) {
+        // Full-system only supports a single thread for the moment.
+        actual_num_threads = 1;
+    } else {
+        actual_num_threads =
+            (numThreads >= workload.size()) ? numThreads : workload.size();
 
-    if (workload.size() == 0) {
-        fatal("Must specify at least one workload!");
+        if (workload.size() == 0) {
+            fatal("Must specify at least one workload!");
+        }
     }
-#endif
 
     numThreads = actual_num_threads;
 
diff --git a/src/cpu/inorder/params.hh b/src/cpu/inorder/params.hh
index 51b7409ad..44f2a5018 100644
--- a/src/cpu/inorder/params.hh
+++ b/src/cpu/inorder/params.hh
@@ -50,10 +50,8 @@ class InOrderParams : public BaseCPU::Params
   public:
 
     // Workloads
-#if !FULL_SYSTEM
     std::vector<Process *> workload;
     Process *process;
-#endif // FULL_SYSTEM
 
     //
     // Memory System/Caches
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc
index 73dd9c527..90ed83d68 100644
--- a/src/cpu/inorder/resources/cache_unit.cc
+++ b/src/cpu/inorder/resources/cache_unit.cc
@@ -150,14 +150,11 @@ CacheUnit::CachePort::setPeer(Port *port)
 {
     Port::setPeer(port);
 
-#if FULL_SYSTEM
     // Update the ThreadContext's memory ports (Functional/Virtual
     // Ports)
     if (cachePortUnit->resName == "dcache_port") {
         cachePortUnit->cpu->updateMemPorts();
     }
-
-#endif
 }
 
 Port *
@@ -454,13 +451,11 @@ CacheUnit::doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size,
     }
 }
 
-#if !FULL_SYSTEM
 void
 CacheUnit::trap(Fault fault, ThreadID tid, DynInstPtr inst)
 {
     tlbBlocked[tid] = false;
 }
-#endif
 
 Fault
 CacheUnit::read(DynInstPtr inst, Addr addr,
diff --git a/src/cpu/inorder/resources/cache_unit.hh b/src/cpu/inorder/resources/cache_unit.hh
index 6bb5868b1..a8dde512b 100644
--- a/src/cpu/inorder/resources/cache_unit.hh
+++ b/src/cpu/inorder/resources/cache_unit.hh
@@ -158,9 +158,8 @@ class CacheUnit : public Resource
 
     bool processSquash(CacheReqPacket *cache_pkt);
 
-#if !FULL_SYSTEM
     void trap(Fault fault, ThreadID tid, DynInstPtr inst);
-#endif
+
     void recvRetry();
 
     /** Returns a specific port. */
diff --git a/src/cpu/inorder/resources/execution_unit.cc b/src/cpu/inorder/resources/execution_unit.cc
index a0a486269..16f737308 100644
--- a/src/cpu/inorder/resources/execution_unit.cc
+++ b/src/cpu/inorder/resources/execution_unit.cc
@@ -38,6 +38,7 @@
 #include "debug/Fault.hh"
 #include "debug/InOrderExecute.hh"
 #include "debug/InOrderStall.hh"
+#include "sim/full_system.hh"
 
 using namespace std;
 using namespace ThePipeline;
@@ -219,14 +220,14 @@ ExecutionUnit::execute(int slot_num)
                                     seq_num, didx, inst->readIntResult(didx));
 #endif
 
-#if !FULL_SYSTEM
-                    // The Syscall might change the PC, so conservatively
-                    // squash everything behing it
-                    if (inst->isSyscall()) {
-                        inst->setSquashInfo(stage_num);
-                        setupSquash(inst, stage_num, tid);
+                    if (!FullSystem) {
+                        // The Syscall might change the PC, so conservatively
+                        // squash everything behing it
+                        if (inst->isSyscall()) {
+                            inst->setSquashInfo(stage_num);
+                            setupSquash(inst, stage_num, tid);
+                        }
                     }
-#endif
                 } else {
                     DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: had a %s "
                             "fault.\n", inst->readTid(), seq_num, fault->name());
diff --git a/src/cpu/inorder/thread_context.cc b/src/cpu/inorder/thread_context.cc
index ecdb61f1f..5f141a1b3 100644
--- a/src/cpu/inorder/thread_context.cc
+++ b/src/cpu/inorder/thread_context.cc
@@ -34,6 +34,7 @@
 #include "cpu/inorder/thread_context.hh"
 #include "cpu/exetrace.hh"
 #include "debug/InOrderCPU.hh"
+#include "sim/full_system.hh"
 
 using namespace TheISA;
 
@@ -88,9 +89,7 @@ InOrderThreadContext::takeOverFrom(ThreadContext *old_context)
     setStatus(old_context->status());
     copyArchRegs(old_context);
 
-#if !FULL_SYSTEM
     thread->funcExeInst = old_context->readFuncExeInst();
-#endif
  
     old_context->setStatus(ThreadContext::Halted);
 
@@ -143,11 +142,10 @@ InOrderThreadContext::halt(int delay)
 void
 InOrderThreadContext::regStats(const std::string &name)
 {
-#if FULL_SYSTEM
-    thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
-    thread->kernelStats->regStats(name + ".kern");
-#endif
-    ;
+    if (FullSystem) {
+        thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
+        thread->kernelStats->regStats(name + ".kern");
+    }
 }
 
 
diff --git a/src/cpu/inorder/thread_context.hh b/src/cpu/inorder/thread_context.hh
index daba6e6b6..84d62137e 100644
--- a/src/cpu/inorder/thread_context.hh
+++ b/src/cpu/inorder/thread_context.hh
@@ -109,11 +109,9 @@ class InOrderThreadContext : public ThreadContext
 
     void setNextMicroPC(uint64_t val) { };
 
-#if FULL_SYSTEM
     /** Returns a pointer to physical memory. */
     PhysicalMemory *getPhysMemPtr()
     { assert(0); return 0; /*return cpu->physmem;*/ }
-#endif
 
     /** Returns a pointer to this thread's kernel statistics. */
     TheISA::Kernel::Statistics *getKernelStats()
diff --git a/src/cpu/inorder/thread_state.hh b/src/cpu/inorder/thread_state.hh
index fc5158d4f..1ffc59f65 100644
--- a/src/cpu/inorder/thread_state.hh
+++ b/src/cpu/inorder/thread_state.hh
@@ -39,17 +39,13 @@
 #include "cpu/thread_state.hh"
 #include "sim/sim_exit.hh"
 
-class Event;
-class InOrderCPU;
-
-#if FULL_SYSTEM
 class EndQuiesceEvent;
-class FunctionProfile;
-class ProfileNode;
-#else
+class Event;
 class FunctionalMemory;
-#endif
+class FunctionProfile;
+class InOrderCPU;
 class Process;
+class ProfileNode;
 
 /**
  * Class that has various thread state, such as the status, the
diff --git a/src/cpu/intr_control.cc b/src/cpu/intr_control.cc
index 62be4ea19..8f3808889 100644
--- a/src/cpu/intr_control.cc
+++ b/src/cpu/intr_control.cc
@@ -48,27 +48,19 @@ IntrControl::IntrControl(const Params *p)
 void
 IntrControl::post(int cpu_id, int int_num, int index)
 {
-#if FULL_SYSTEM
     DPRINTF(IntrControl, "post  %d:%d (cpu %d)\n", int_num, index, cpu_id);
     std::vector<ThreadContext *> &tcvec = sys->threadContexts;
     BaseCPU *cpu = tcvec[cpu_id]->getCpuPtr();
     cpu->postInterrupt(int_num, index);
-#else
-    panic("Called IntrControl::post in SE mode.\n");
-#endif
 }
 
 void
 IntrControl::clear(int cpu_id, int int_num, int index)
 {
-#if FULL_SYSTEM
     DPRINTF(IntrControl, "clear %d:%d (cpu %d)\n", int_num, index, cpu_id);
     std::vector<ThreadContext *> &tcvec = sys->threadContexts;
     BaseCPU *cpu = tcvec[cpu_id]->getCpuPtr();
     cpu->clearInterrupt(int_num, index);
-#else
-    panic("Called IntrControl::clear in SE mode.\n");
-#endif
 }
 
 IntrControl *
diff --git a/src/cpu/legiontrace.cc b/src/cpu/legiontrace.cc
index 484af1008..5e4c978a6 100644
--- a/src/cpu/legiontrace.cc
+++ b/src/cpu/legiontrace.cc
@@ -36,11 +36,6 @@
     #error Legion tracing only works with SPARC simulations!
 #endif
 
-#include "config/full_system.hh"
-#if !FULL_SYSTEM
-    #error Legion tracing only works in full system!
-#endif
-
 #include <sys/ipc.h>
 #include <sys/shm.h>
 
@@ -50,28 +45,24 @@
 #include "arch/sparc/predecoder.hh"
 #include "arch/sparc/registers.hh"
 #include "arch/sparc/utility.hh"
+#include "arch/tlb.hh"
 #include "base/socket.hh"
 #include "cpu/base.hh"
 #include "cpu/decode.hh"
 #include "cpu/legiontrace.hh"
 #include "cpu/static_inst.hh"
 #include "cpu/thread_context.hh"
+#include "sim/full_system.hh"
 #include "sim/system.hh"
 
-#if FULL_SYSTEM
-#include "arch/tlb.hh"
-#endif
-
 //XXX This is temporary
 #include "cpu/m5legion_interface.h"
 
 using namespace std;
 using namespace TheISA;
 
-#if FULL_SYSTEM
 static int diffcount = 0;
 static bool wasMicro = false;
-#endif
 
 namespace Trace {
 SharedData *shared_data = NULL;
@@ -597,5 +588,7 @@ Trace::LegionTraceRecord::dump()
 Trace::LegionTrace *
 LegionTraceParams::create()
 {
+    if (!FullSystem)
+        panic("Legion tracing only works in full system!");
     return new Trace::LegionTrace(this);
 };
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py
index 47b18a3ec..51643c169 100644
--- a/src/cpu/o3/O3CPU.py
+++ b/src/cpu/o3/O3CPU.py
@@ -40,15 +40,11 @@ class DerivO3CPU(BaseCPU):
     activity = Param.Unsigned(0, "Initial count")
 
     if buildEnv['USE_CHECKER']:
-        if not buildEnv['FULL_SYSTEM']:
-            checker = Param.BaseCPU(O3Checker(workload=Parent.workload,
-                                              exitOnError=False,
-                                              updateOnError=True,
-                                              warnOnlyOnLoadError=False),
-                                    "checker")
-        else:
-            checker = Param.BaseCPU(O3Checker(exitOnError=False, updateOnError=True,
-                                              warnOnlyOnLoadError=False), "checker")
+        checker = Param.BaseCPU(O3Checker(workload=Parent.workload,
+                                          exitOnError=False,
+                                          updateOnError=True,
+                                          warnOnlyOnLoadError=False),
+                                "checker")
         checker.itb = Parent.itb
         checker.dtb = Parent.dtb
 
diff --git a/src/cpu/o3/checker_builder.cc b/src/cpu/o3/checker_builder.cc
index 5d0bd2ed2..b34613f68 100644
--- a/src/cpu/o3/checker_builder.cc
+++ b/src/cpu/o3/checker_builder.cc
@@ -90,11 +90,8 @@ O3CheckerParams::create()
     params->dtb = dtb;
     params->system = system;
     params->cpu_id = cpu_id;
-#if FULL_SYSTEM
     params->profile = profile;
-#else
     params->process = workload;
-#endif
 
     O3Checker *cpu = new O3Checker(params);
     return cpu;
diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index ffc2c16d2..b45d37df9 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -267,13 +267,11 @@ class DefaultCommit
     void squashAfter(ThreadID tid, DynInstPtr &head_inst,
             uint64_t squash_after_seq_num);
 
-#if FULL_SYSTEM
     /** Handles processing an interrupt. */
     void handleInterrupt();
 
     /** Get fetch redirecting so we can handle an interrupt */
     void propagateInterrupt();
-#endif // FULL_SYSTEM
 
     /** Commits as many instructions as possible. */
     void commitInsts();
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 75ae87c75..c481d7b9c 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -47,7 +47,6 @@
 #include "arch/utility.hh"
 #include "base/loader/symtab.hh"
 #include "base/cp_annotate.hh"
-#include "config/full_system.hh"
 #include "config/the_isa.hh"
 #include "config/use_checker.hh"
 #include "cpu/o3/commit.hh"
@@ -61,6 +60,7 @@
 #include "debug/O3PipeView.hh"
 #include "params/DerivO3CPU.hh"
 #include "sim/faults.hh"
+#include "sim/full_system.hh"
 
 #if USE_CHECKER
 #include "cpu/checker/cpu.hh"
@@ -148,9 +148,7 @@ DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
         pc[tid].set(0);
         lastCommitedSeqNum[tid] = 0;
     }
-#if FULL_SYSTEM
     interrupt = NoFault;
-#endif
 }
 
 template <class Impl>
@@ -700,7 +698,6 @@ DefaultCommit<Impl>::tick()
     updateStatus();
 }
 
-#if FULL_SYSTEM
 template <class Impl>
 void
 DefaultCommit<Impl>::handleInterrupt()
@@ -766,22 +763,20 @@ DefaultCommit<Impl>::propagateInterrupt()
         toIEW->commitInfo[0].interruptPending = true;
 }
 
-#endif // FULL_SYSTEM
-
 template <class Impl>
 void
 DefaultCommit<Impl>::commit()
 {
-
-#if FULL_SYSTEM
-    // Check for any interrupt that we've already squashed for and start processing it.
-    if (interrupt != NoFault)
-        handleInterrupt();
-
-    // Check if we have a interrupt and get read to handle it
-    if (cpu->checkInterrupts(cpu->tcBase(0)))
-        propagateInterrupt();
-#endif // FULL_SYSTEM
+    if (FullSystem) {
+        // Check for any interrupt that we've already squashed for and start
+        // processing it.
+        if (interrupt != NoFault)
+            handleInterrupt();
+
+        // Check if we have a interrupt and get read to handle it
+        if (cpu->checkInterrupts(cpu->tcBase(0)))
+            propagateInterrupt();
+    }
 
     ////////////////////////////////////
     // Check for any possible squashes, handle them first
@@ -1173,22 +1168,22 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
 
     updateComInstStats(head_inst);
 
-#if FULL_SYSTEM
-    if (thread[tid]->profile) {
-        thread[tid]->profilePC = head_inst->instAddr();
-        ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
-                                                          head_inst->staticInst);
+    if (FullSystem) {
+        if (thread[tid]->profile) {
+            thread[tid]->profilePC = head_inst->instAddr();
+            ProfileNode *node = thread[tid]->profile->consume(
+                    thread[tid]->getTC(), head_inst->staticInst);
 
-        if (node)
-            thread[tid]->profileNode = node;
-    }
-    if (CPA::available()) {
-        if (head_inst->isControl()) {
-            ThreadContext *tc = thread[tid]->getTC();
-            CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
+            if (node)
+                thread[tid]->profileNode = node;
+        }
+        if (CPA::available()) {
+            if (head_inst->isControl()) {
+                ThreadContext *tc = thread[tid]->getTC();
+                CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
+            }
         }
     }
-#endif
     DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n",
             head_inst->seqNum, head_inst->pcState());
     if (head_inst->traceData) {
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 08cf0a692..16e78f8ec 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -32,7 +32,6 @@
  */
 
 #include "arch/kernel_stats.hh"
-#include "config/full_system.hh"
 #include "config/the_isa.hh"
 #include "config/use_checker.hh"
 #include "cpu/o3/cpu.hh"
@@ -47,6 +46,7 @@
 #include "debug/Quiesce.hh"
 #include "enums/MemoryMode.hh"
 #include "sim/core.hh"
+#include "sim/full_system.hh"
 #include "sim/process.hh"
 #include "sim/stat_control.hh"
 #include "sim/system.hh"
@@ -215,18 +215,16 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
     if (params->checker) {
         BaseCPU *temp_checker = params->checker;
         checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
-#if FULL_SYSTEM
         checker->setSystem(params->system);
-#endif
     } else {
         checker = NULL;
     }
 #endif // USE_CHECKER
 
-#if !FULL_SYSTEM
-    thread.resize(numThreads);
-    tids.resize(numThreads);
-#endif
+    if (!FullSystem) {
+        thread.resize(numThreads);
+        tids.resize(numThreads);
+    }
 
     // The stages also need their CPU pointer setup.  However this
     // must be done at the upper level CPU because they have pointers
@@ -262,17 +260,18 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
     rename.setIEWStage(&iew);
     rename.setCommitStage(&commit);
 
-#if !FULL_SYSTEM
-    ThreadID active_threads = params->workload.size();
+    ThreadID active_threads;
+    if (FullSystem) {
+        active_threads = 1;
+    } else {
+        active_threads = params->workload.size();
 
-    if (active_threads > Impl::MaxThreads) {
-        panic("Workload Size too large. Increase the 'MaxThreads'"
-              "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or "
-              "edit your workload size.");
+        if (active_threads > Impl::MaxThreads) {
+            panic("Workload Size too large. Increase the 'MaxThreads' "
+                  "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) "
+                  "or edit your workload size.");
+        }
     }
-#else
-    ThreadID active_threads = 1;
-#endif
 
     //Make Sure That this a Valid Architeture
     assert(params->numPhysIntRegs   >= numThreads * TheISA::NumIntRegs);
@@ -351,31 +350,31 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
     this->thread.resize(this->numThreads);
 
     for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
-#if FULL_SYSTEM
-        // SMT is not supported in FS mode yet.
-        assert(this->numThreads == 1);
-        this->thread[tid] = new Thread(this, 0, NULL);
-#else
-        if (tid < params->workload.size()) {
-            DPRINTF(O3CPU, "Workload[%i] process is %#x",
-                    tid, this->thread[tid]);
-            this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
-                    (typename Impl::O3CPU *)(this),
-                    tid, params->workload[tid]);
-
-            //usedTids[tid] = true;
-            //threadMap[tid] = tid;
+        if (FullSystem) {
+            // SMT is not supported in FS mode yet.
+            assert(this->numThreads == 1);
+            this->thread[tid] = new Thread(this, 0, NULL);
         } else {
-            //Allocate Empty thread so M5 can use later
-            //when scheduling threads to CPU
-            Process* dummy_proc = NULL;
-
-            this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
-                    (typename Impl::O3CPU *)(this),
-                    tid, dummy_proc);
-            //usedTids[tid] = false;
+            if (tid < params->workload.size()) {
+                DPRINTF(O3CPU, "Workload[%i] process is %#x",
+                        tid, this->thread[tid]);
+                this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
+                        (typename Impl::O3CPU *)(this),
+                        tid, params->workload[tid]);
+
+                //usedTids[tid] = true;
+                //threadMap[tid] = tid;
+            } else {
+                //Allocate Empty thread so M5 can use later
+                //when scheduling threads to CPU
+                Process* dummy_proc = NULL;
+
+                this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
+                        (typename Impl::O3CPU *)(this),
+                        tid, dummy_proc);
+                //usedTids[tid] = false;
+            }
         }
-#endif // !FULL_SYSTEM
 
         ThreadContext *tc;
 
@@ -397,10 +396,10 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
         assert(o3_tc->cpu);
         o3_tc->thread = this->thread[tid];
 
-#if FULL_SYSTEM
-        // Setup quiesce event.
-        this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
-#endif
+        if (FullSystem) {
+            // Setup quiesce event.
+            this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
+        }
         // Give the thread the TC.
         this->thread[tid]->tc = tc;
 
@@ -547,9 +546,8 @@ FullO3CPU<Impl>::tick()
 
     commit.tick();
 
-#if !FULL_SYSTEM
-    doContextSwitch();
-#endif
+    if (!FullSystem)
+        doContextSwitch();
 
     // Now advance the time buffers
     timeBuffer.advance();
@@ -581,9 +579,8 @@ FullO3CPU<Impl>::tick()
         }
     }
 
-#if !FULL_SYSTEM
-    updateThreadPriority();
-#endif
+    if (!FullSystem)
+        updateThreadPriority();
 }
 
 template <class Impl>
@@ -597,12 +594,12 @@ FullO3CPU<Impl>::init()
     for (ThreadID tid = 0; tid < numThreads; ++tid)
         thread[tid]->inSyscall = true;
 
-#if FULL_SYSTEM
-    for (ThreadID tid = 0; tid < numThreads; tid++) {
-        ThreadContext *src_tc = threadContexts[tid];
-        TheISA::initCPU(src_tc, src_tc->contextId());
+    if (FullSystem) {
+        for (ThreadID tid = 0; tid < numThreads; tid++) {
+            ThreadContext *src_tc = threadContexts[tid];
+            TheISA::initCPU(src_tc, src_tc->contextId());
+        }
     }
-#endif
 
     // Clear inSyscall.
     for (int tid = 0; tid < numThreads; ++tid)
@@ -738,11 +735,11 @@ FullO3CPU<Impl>::insertThread(ThreadID tid)
     DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
     // Will change now that the PC and thread state is internal to the CPU
     // and not in the ThreadContext.
-#if FULL_SYSTEM
-    ThreadContext *src_tc = system->threadContexts[tid];
-#else
-    ThreadContext *src_tc = tcBase(tid);
-#endif
+    ThreadContext *src_tc;
+    if (FullSystem)
+        src_tc = system->threadContexts[tid];
+    else
+        src_tc = tcBase(tid);
 
     //Bind Int Regs to Rename Map
     for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
diff --git a/src/cpu/o3/cpu_builder.cc b/src/cpu/o3/cpu_builder.cc
index 097dc7181..82df345bd 100644
--- a/src/cpu/o3/cpu_builder.cc
+++ b/src/cpu/o3/cpu_builder.cc
@@ -47,22 +47,23 @@ class DerivO3CPU : public FullO3CPU<O3CPUImpl>
 DerivO3CPU *
 DerivO3CPUParams::create()
 {
-#if FULL_SYSTEM
-    // Full-system only supports a single thread for the moment.
-    ThreadID actual_num_threads = 1;
-#else
-    if (workload.size() > numThreads) {
-        fatal("Workload Size (%i) > Max Supported Threads (%i) on This CPU",
-              workload.size(), numThreads);
-    } else if (workload.size() == 0) {
-        fatal("Must specify at least one workload!");
+    ThreadID actual_num_threads;
+    if (FullSystem) {
+        // Full-system only supports a single thread for the moment.
+        actual_num_threads = 1;
+    } else {
+        if (workload.size() > numThreads) {
+            fatal("Workload Size (%i) > Max Supported Threads (%i) on This CPU",
+                  workload.size(), numThreads);
+        } else if (workload.size() == 0) {
+            fatal("Must specify at least one workload!");
+        }
+
+        // In non-full-system mode, we infer the number of threads from
+        // the workload if it's not explicitly specified.
+        actual_num_threads =
+            (numThreads >= workload.size()) ? numThreads : workload.size();
     }
-    
-    // In non-full-system mode, we infer the number of threads from
-    // the workload if it's not explicitly specified.
-    ThreadID actual_num_threads =
-        (numThreads >= workload.size()) ? numThreads : workload.size();
-#endif
 
     numThreads = actual_num_threads;
 
diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh
index 0c0ec768e..3def971e9 100644
--- a/src/cpu/o3/decode_impl.hh
+++ b/src/cpu/o3/decode_impl.hh
@@ -30,13 +30,13 @@
 
 #include "arch/types.hh"
 #include "base/trace.hh"
-#include "config/full_system.hh"
 #include "config/the_isa.hh"
 #include "cpu/o3/decode.hh"
 #include "cpu/inst_seq.hh"
 #include "debug/Activity.hh"
 #include "debug/Decode.hh"
 #include "params/DerivO3CPU.hh"
+#include "sim/full_system.hh"
 
 using namespace std;
 
@@ -322,19 +322,18 @@ DefaultDecode<Impl>::squash(ThreadID tid)
 
     if (decodeStatus[tid] == Blocked ||
         decodeStatus[tid] == Unblocking) {
-#if !FULL_SYSTEM
-        // In syscall emulation, we can have both a block and a squash due
-        // to a syscall in the same cycle.  This would cause both signals to
-        // be high.  This shouldn't happen in full system.
-        // @todo: Determine if this still happens.
-        if (toFetch->decodeBlock[tid]) {
-            toFetch->decodeBlock[tid] = 0;
-        } else {
+        if (FullSystem) {
             toFetch->decodeUnblock[tid] = 1;
+        } else {
+            // In syscall emulation, we can have both a block and a squash due
+            // to a syscall in the same cycle.  This would cause both signals
+            // to be high.  This shouldn't happen in full system.
+            // @todo: Determine if this still happens.
+            if (toFetch->decodeBlock[tid])
+                toFetch->decodeBlock[tid] = 0;
+            else
+                toFetch->decodeUnblock[tid] = 1;
         }
-#else
-        toFetch->decodeUnblock[tid] = 1;
-#endif
     }
 
     // Set status to squashing.
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index b0ec349dc..686b40dc5 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -45,7 +45,9 @@
 #include <cstring>
 
 #include "arch/isa_traits.hh"
+#include "arch/tlb.hh"
 #include "arch/utility.hh"
+#include "arch/vtophys.hh"
 #include "base/types.hh"
 #include "config/the_isa.hh"
 #include "config/use_checker.hh"
@@ -61,12 +63,8 @@
 #include "sim/byteswap.hh"
 #include "sim/core.hh"
 #include "sim/eventq.hh"
-
-#if FULL_SYSTEM
-#include "arch/tlb.hh"
-#include "arch/vtophys.hh"
+#include "sim/full_system.hh"
 #include "sim/system.hh"
-#endif // FULL_SYSTEM
 
 using namespace std;
 
@@ -907,15 +905,15 @@ DefaultFetch<Impl>::tick()
 
     DPRINTF(Fetch, "Running stage.\n");
 
-    #if FULL_SYSTEM
-    if (fromCommit->commitInfo[0].interruptPending) {
-        interruptPending = true;
-    }
+    if (FullSystem) {
+        if (fromCommit->commitInfo[0].interruptPending) {
+            interruptPending = true;
+        }
 
-    if (fromCommit->commitInfo[0].clearInterrupt) {
-        interruptPending = false;
+        if (fromCommit->commitInfo[0].clearInterrupt) {
+            interruptPending = false;
+        }
     }
-#endif
 
     for (threadFetched = 0; threadFetched < numFetchingThreads;
          threadFetched++) {
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index 14917bc16..1fcd73ba1 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -334,10 +334,8 @@ class LSQ {
     /** D-cache port. */
     DcachePort dcachePort;
 
-#if FULL_SYSTEM
     /** Tell the CPU to update the Phys and Virt ports. */
     void updateMemPorts() { cpu->updateMemPorts(); }
-#endif
 
   protected:
     /** The LSQ policy for SMT mode. */
diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index ef9167d8c..8b1638c70 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -46,11 +46,9 @@ LSQ<Impl>::DcachePort::setPeer(Port *port)
 {
     Port::setPeer(port);
 
-#if FULL_SYSTEM
     // Update the ThreadContext's memory ports (Functional/Virtual
     // Ports)
     lsq->updateMemPorts();
-#endif
 }
 
 template <class Impl>
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index d04f45cc0..ec3a252fd 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -35,6 +35,7 @@
 #include <vector>
 
 #include "arch/isa_traits.hh"
+#include "arch/kernel_stats.hh"
 #include "arch/types.hh"
 #include "base/trace.hh"
 #include "config/full_system.hh"
@@ -42,10 +43,6 @@
 #include "cpu/o3/comm.hh"
 #include "debug/IEW.hh"
 
-#if FULL_SYSTEM
-#include "arch/kernel_stats.hh"
-#endif
-
 /**
  * Simple physical register file class.
  * Right now this is specific to Alpha until we decide if/how to make things
@@ -174,10 +171,8 @@ class PhysRegFile
     /** Floating point register file. */
     PhysFloatReg *floatRegFile;
 
-#if FULL_SYSTEM
   private:
     int intrflag;                       // interrupt flag
-#endif
 
   private:
     /** CPU pointer. */
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index a49440f1f..15fc397dc 100755
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -41,6 +41,7 @@
  *          Korey Sewell
  */
 
+#include "arch/kernel_stats.hh"
 #include "arch/registers.hh"
 #include "config/the_isa.hh"
 #include "cpu/o3/thread_context.hh"
@@ -66,9 +67,7 @@ void
 O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
 {
     // some things should already be set up
-#if FULL_SYSTEM
     assert(getSystemPtr() == old_context->getSystemPtr());
-#endif
     assert(getProcessPtr() == old_context->getProcessPtr());
 
     // copy over functional state
@@ -77,24 +76,23 @@ O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
     setContextId(old_context->contextId());
     setThreadId(old_context->threadId());
 
-#if !FULL_SYSTEM
-    thread->funcExeInst = old_context->readFuncExeInst();
-#else
-    EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
-    if (other_quiesce) {
-        // Point the quiesce event's TC at this TC so that it wakes up
-        // the proper CPU.
-        other_quiesce->tc = this;
+    if (FullSystem) {
+        EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
+        if (other_quiesce) {
+            // Point the quiesce event's TC at this TC so that it wakes up
+            // the proper CPU.
+            other_quiesce->tc = this;
+        }
+        if (thread->quiesceEvent) {
+            thread->quiesceEvent->tc = this;
+        }
+
+        // Transfer kernel stats from one CPU to the other.
+        thread->kernelStats = old_context->getKernelStats();
+        cpu->lockFlag = false;
+    } else {
+        thread->funcExeInst = old_context->readFuncExeInst();
     }
-    if (thread->quiesceEvent) {
-        thread->quiesceEvent->tc = this;
-    }
-
-    // Transfer kernel stats from one CPU to the other.
-    thread->kernelStats = old_context->getKernelStats();
-//    storeCondFailures = 0;
-    cpu->lockFlag = false;
-#endif
 
     old_context->setStatus(ThreadContext::Halted);
 
@@ -112,10 +110,7 @@ O3ThreadContext<Impl>::activate(int delay)
     if (thread->status() == ThreadContext::Active)
         return;
 
-#if FULL_SYSTEM
     thread->lastActivate = curTick();
-#endif
-
     thread->setStatus(ThreadContext::Active);
 
     // status() == Suspended
@@ -132,19 +127,9 @@ O3ThreadContext<Impl>::suspend(int delay)
     if (thread->status() == ThreadContext::Suspended)
         return;
 
-#if FULL_SYSTEM
     thread->lastActivate = curTick();
     thread->lastSuspend = curTick();
-#endif
-/*
-#if FULL_SYSTEM
-    // Don't change the status from active if there are pending interrupts
-    if (cpu->checkInterrupts()) {
-        assert(status() == ThreadContext::Active);
-        return;
-    }
-#endif
-*/
+
     thread->setStatus(ThreadContext::Suspended);
     cpu->suspendContext(thread->threadId());
 }
@@ -167,32 +152,26 @@ template <class Impl>
 void
 O3ThreadContext<Impl>::regStats(const std::string &name)
 {
-#if FULL_SYSTEM
-    thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
-    thread->kernelStats->regStats(name + ".kern");
-#endif
+    if (FullSystem) {
+        thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
+        thread->kernelStats->regStats(name + ".kern");
+    }
 }
 
 template <class Impl>
 void
 O3ThreadContext<Impl>::serialize(std::ostream &os)
 {
-#if FULL_SYSTEM
-    if (thread->kernelStats)
+    if (FullSystem && thread->kernelStats)
         thread->kernelStats->serialize(os);
-#endif
-
 }
 
 template <class Impl>
 void
 O3ThreadContext<Impl>::unserialize(Checkpoint *cp, const std::string &section)
 {
-#if FULL_SYSTEM
-    if (thread->kernelStats)
+    if (FullSystem && thread->kernelStats)
         thread->kernelStats->unserialize(cp, section);
-#endif
-
 }
 
 template <class Impl>
@@ -232,9 +211,8 @@ O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc)
     TheISA::copyRegs(tc, this);
     thread->inSyscall = false;
 
-#if !FULL_SYSTEM
-    this->thread->funcExeInst = tc->readFuncExeInst();
-#endif
+    if (!FullSystem)
+        this->thread->funcExeInst = tc->readFuncExeInst();
 }
 
 template <class Impl>
diff --git a/src/cpu/o3/thread_state.hh b/src/cpu/o3/thread_state.hh
index 1d58e2b27..fc54ec33c 100644
--- a/src/cpu/o3/thread_state.hh
+++ b/src/cpu/o3/thread_state.hh
@@ -35,6 +35,7 @@
 #include "base/output.hh"
 #include "cpu/thread_context.hh"
 #include "cpu/thread_state.hh"
+#include "sim/full_system.hh"
 #include "sim/sim_exit.hh"
 
 class EndQuiesceEvent;
@@ -74,21 +75,22 @@ struct O3ThreadState : public ThreadState {
         : ThreadState(_cpu, _thread_num, _process),
           cpu(_cpu), inSyscall(0), trapPending(0)
     {
-#if FULL_SYSTEM
-        if (cpu->params()->profile) {
-            profile = new FunctionProfile(cpu->params()->system->kernelSymtab);
-            Callback *cb =
-                new MakeCallback<O3ThreadState,
-                &O3ThreadState::dumpFuncProfile>(this);
-            registerExitCallback(cb);
-        }
+        if (FullSystem) {
+            if (cpu->params()->profile) {
+                profile = new FunctionProfile(
+                        cpu->params()->system->kernelSymtab);
+                Callback *cb =
+                    new MakeCallback<O3ThreadState,
+                    &O3ThreadState::dumpFuncProfile>(this);
+                registerExitCallback(cb);
+            }
 
-        // let's fill with a dummy node for now so we don't get a segfault
-        // on the first cycle when there's no node available.
-        static ProfileNode dummyNode;
-        profileNode = &dummyNode;
-        profilePC = 3;
-#endif
+            // let's fill with a dummy node for now so we don't get a segfault
+            // on the first cycle when there's no node available.
+            static ProfileNode dummyNode;
+            profileNode = &dummyNode;
+            profilePC = 3;
+        }
     }
 
     /** Pointer to the ThreadContext of this thread. */
diff --git a/src/cpu/ozone/SimpleOzoneCPU.py b/src/cpu/ozone/SimpleOzoneCPU.py
index d4620cd8e..d79418b27 100644
--- a/src/cpu/ozone/SimpleOzoneCPU.py
+++ b/src/cpu/ozone/SimpleOzoneCPU.py
@@ -35,8 +35,7 @@ class SimpleOzoneCPU(BaseCPU):
 
     numThreads = Param.Unsigned("number of HW thread contexts")
 
-    if not buildEnv['FULL_SYSTEM']:
-        mem = Param.FunctionalMemory(NULL, "memory")
+    mem = Param.FunctionalMemory(NULL, "memory")
 
     width = Param.Unsigned("Width")
     frontEndWidth = Param.Unsigned("Front end width")
diff --git a/src/cpu/ozone/back_end_impl.hh b/src/cpu/ozone/back_end_impl.hh
index 169f328ad..1df0cdf0e 100644
--- a/src/cpu/ozone/back_end_impl.hh
+++ b/src/cpu/ozone/back_end_impl.hh
@@ -1456,7 +1456,6 @@ BackEnd<Impl>::commitInst(int inst_num)
 //        thread->funcExeInst--;
 
         if (inst->isNonSpeculative()) {
-#if !FULL_SYSTEM
             // Hack to make sure syscalls aren't executed until all stores
             // write back their data.  This direct communication shouldn't
             // be used for anything other than this.
@@ -1464,7 +1463,6 @@ BackEnd<Impl>::commitInst(int inst_num)
                 DPRINTF(BE, "Waiting for all stores to writeback.\n");
                 return false;
             }
-#endif
 
             DPRINTF(BE, "Encountered a store or non-speculative "
                     "instruction at the head of the ROB, PC %#x.\n",
@@ -1512,7 +1510,6 @@ BackEnd<Impl>::commitInst(int inst_num)
 
     if (inst_fault != NoFault) {
         if (!inst->isNop()) {
-#if FULL_SYSTEM
             DPRINTF(BE, "Inst [sn:%lli] PC %#x has a fault\n",
                     inst->seqNum, inst->readPC());
 
@@ -1533,10 +1530,6 @@ BackEnd<Impl>::commitInst(int inst_num)
 //            generateTrapEvent();
 
             return false;
-#else // !FULL_SYSTEM
-            panic("fault (%d) detected @ PC %08p", inst_fault,
-                  inst->PC);
-#endif // FULL_SYSTEM
         }
     }
 
@@ -1574,7 +1567,6 @@ BackEnd<Impl>::commitInst(int inst_num)
     // Write the done sequence number here.
     toIEW->doneSeqNum = inst->seqNum;
 
-#if FULL_SYSTEM
     int count = 0;
     Addr oldpc;
     do {
@@ -1591,7 +1583,6 @@ BackEnd<Impl>::commitInst(int inst_num)
 //        squashPending = true;
         return false;
     }
-#endif
     return true;
 }
 
diff --git a/src/cpu/ozone/checker_builder.cc b/src/cpu/ozone/checker_builder.cc
index 6baa95658..f4bb03dcc 100644
--- a/src/cpu/ozone/checker_builder.cc
+++ b/src/cpu/ozone/checker_builder.cc
@@ -91,11 +91,8 @@ OzoneCheckerParams::create()
     params->dtb = dtb;
     params->system = system;
     params->cpu_id = cpu_id;
-#if FULL_SYSTEM
     params->profile = profile;
-#else
     params->process = workload;
-#endif
 
     OzoneChecker *cpu = new OzoneChecker(params);
     return cpu;
diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index 70b46ec5f..3115069bf 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -33,6 +33,7 @@
 
 #include <set>
 
+#include "arch/alpha/tlb.hh"
 #include "base/statistics.hh"
 #include "config/full_system.hh"
 #include "config/the_isa.hh"
@@ -48,31 +49,20 @@
 #include "sim/eventq.hh"
 
 // forward declarations
-#if FULL_SYSTEM
-#include "arch/alpha/tlb.hh"
-
-namespace TheISA
-{
-    class TLB;
-}
-class PhysicalMemory;
-class MemoryController;
 
 namespace TheISA {
     namespace Kernel {
         class Statistics;
     };
+    class TLB;
 };
 
-#else
-
-class Process;
-
-#endif // FULL_SYSTEM
-
 class Checkpoint;
 class EndQuiesceEvent;
+class MemoryController;
 class MemObject;
+class PhysicalMemory;
+class Process;
 class Request;
 
 namespace Trace {
@@ -116,14 +106,13 @@ class OzoneCPU : public BaseCPU
 
         TheISA::TLB * getDTBPtr() { return cpu->dtb; }
 
-#if FULL_SYSTEM
         System *getSystemPtr() { return cpu->system; }
 
         PhysicalMemory *getPhysMemPtr() { return cpu->physmem; }
 
         TheISA::Kernel::Statistics *getKernelStats()
         { return thread->getKernelStats(); }
-#endif
+
         Process *getProcessPtr() { return thread->getProcessPtr(); }
 
         TranslatingPort *getMemPort() { return thread->getMemPort(); }
@@ -147,9 +136,7 @@ class OzoneCPU : public BaseCPU
         /// Set the status to Halted.
         void halt();
 
-#if FULL_SYSTEM
         void dumpFuncProfile();
-#endif
 
         void takeOverFrom(ThreadContext *old_context);
 
@@ -158,7 +145,6 @@ class OzoneCPU : public BaseCPU
         void serialize(std::ostream &os);
         void unserialize(Checkpoint *cp, const std::string &section);
 
-#if FULL_SYSTEM
         EndQuiesceEvent *getQuiesceEvent();
 
         Tick readLastActivate();
@@ -166,7 +152,6 @@ class OzoneCPU : public BaseCPU
 
         void profileClear();
         void profileSample();
-#endif
 
         int threadId();
 
@@ -226,12 +211,10 @@ class OzoneCPU : public BaseCPU
 
         bool misspeculating() { return false; }
 
-#if !FULL_SYSTEM
         Counter readFuncExeInst() { return thread->funcExeInst; }
 
         void setFuncExeInst(Counter new_val)
         { thread->funcExeInst = new_val; }
-#endif
     };
 
     // Ozone specific thread context
@@ -325,7 +308,6 @@ class OzoneCPU : public BaseCPU
 
     int switchCount;
 
-#if FULL_SYSTEM
     Addr dbg_vtophys(Addr addr);
 
     bool interval_stats;
@@ -334,7 +316,6 @@ class OzoneCPU : public BaseCPU
     TheISA::TLB *dtb;
     System *system;
     PhysicalMemory *physmem;
-#endif
 
     virtual Port *getPort(const std::string &name, int idx);
 
@@ -413,13 +394,10 @@ class OzoneCPU : public BaseCPU
 
     void dumpInsts() { frontEnd->dumpInsts(); }
 
-#if FULL_SYSTEM
     Fault hwrei();
     bool simPalCheck(int palFunc);
     void processInterrupts();
-#else
     void syscall(uint64_t &callnum);
-#endif
 
     ThreadContext *tcBase() { return tc; }
 
diff --git a/src/cpu/ozone/cpu_builder.cc b/src/cpu/ozone/cpu_builder.cc
index 63b7eb6ff..65f68152f 100644
--- a/src/cpu/ozone/cpu_builder.cc
+++ b/src/cpu/ozone/cpu_builder.cc
@@ -57,21 +57,20 @@ DerivOzoneCPUParams::create()
 {
     DerivOzoneCPU *cpu;
 
-#if FULL_SYSTEM
-    // Full-system only supports a single thread for the moment.
-    ThreadID actual_num_threads = 1;
-#else
-    // In non-full-system mode, we infer the number of threads from
-    // the workload if it's not explicitly specified.
-    ThreadID actual_num_threads =
-        numThreads.isValid() ? numThreads : workload.size();
-
-    if (workload.size() == 0) {
-        fatal("Must specify at least one workload!");
+    if (FullSystem) {
+        // Full-system only supports a single thread for the moment.
+        ThreadID actual_num_threads = 1;
+    } else {
+        // In non-full-system mode, we infer the number of threads from
+        // the workload if it's not explicitly specified.
+        ThreadID actual_num_threads =
+            numThreads.isValid() ? numThreads : workload.size();
+
+        if (workload.size() == 0) {
+            fatal("Must specify at least one workload!");
+        }
     }
 
-#endif
-
     SimpleParams *params = new SimpleParams;
 
     params->clock = clock;
@@ -84,15 +83,11 @@ DerivOzoneCPUParams::create()
 
     params->system = system;
     params->cpu_id = cpu_id;
-#if FULL_SYSTEM
     params->profile = profile;
     params->do_quiesce = do_quiesce;
     params->do_checkpoint_insts = do_checkpoint_insts;
     params->do_statistics_insts = do_statistics_insts;
-#else
     params->workload = workload;
-//    params->pTable = page_table;
-#endif // FULL_SYSTEM
 
     params->checker = checker;
     params->max_insts_any_thread = max_insts_any_thread;
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index 724bd99a4..e2f5dc10c 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -29,37 +29,33 @@
  *          Nathan Binkert
  */
 
+#include "arch/alpha/osfpal.hh"
+#include "arch/faults.hh"
 #include "arch/isa_traits.hh" // For MachInst
+#include "arch/kernel_stats.hh"
+#include "arch/tlb.hh"
+#include "arch/types.hh"
+#include "arch/vtophys.hh"
+#include "base/callback.hh"
 #include "base/trace.hh"
-#include "config/full_system.hh"
 #include "config/the_isa.hh"
 #include "config/use_checker.hh"
 #include "cpu/ozone/cpu.hh"
 #include "cpu/base.hh"
 #include "cpu/exetrace.hh"
+#include "cpu/profile.hh"
 #include "cpu/quiesce_event.hh"
 #include "cpu/simple_thread.hh"
 #include "cpu/static_inst.hh"
 #include "cpu/thread_context.hh"
-#include "sim/sim_object.hh"
-#include "sim/stats.hh"
-
-#if FULL_SYSTEM
-#include "arch/alpha/osfpal.hh"
-#include "arch/faults.hh"
-#include "arch/kernel_stats.hh"
-#include "arch/tlb.hh"
-#include "arch/types.hh"
-#include "arch/vtophys.hh"
-#include "base/callback.hh"
-#include "cpu/profile.hh"
 #include "sim/faults.hh"
+#include "sim/full_system.hh"
+#include "sim/process.hh"
 #include "sim/sim_events.hh"
 #include "sim/sim_exit.hh"
+#include "sim/sim_object.hh"
+#include "sim/stats.hh"
 #include "sim/system.hh"
-#else // !FULL_SYSTEM
-#include "sim/process.hh"
-#endif // FULL_SYSTEM
 
 #if USE_CHECKER
 #include "cpu/checker/thread_context.hh"
@@ -89,12 +85,8 @@ OzoneCPU<Impl>::TickEvent::description() const
 
 template <class Impl>
 OzoneCPU<Impl>::OzoneCPU(Params *p)
-#if FULL_SYSTEM
-    : BaseCPU(p), thread(this, 0), tickEvent(this, p->width),
-#else
-    : BaseCPU(p), thread(this, 0, p->workload[0], 0),
-      tickEvent(this, p->width),
-#endif
+    : BaseCPU(p), thread(this, 0, p->workload[0], 0), tickEvent(this,
+            p->width),
 #ifndef NDEBUG
       instcount(0),
 #endif
@@ -109,9 +101,7 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
 #if USE_CHECKER
         BaseCPU *temp_checker = p->checker;
         checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
-#if FULL_SYSTEM
         checker->setSystem(p->system);
-#endif
         checkerTC = new CheckerThreadContext<OzoneTC>(&ozoneTC, checker);
         thread.tc = checkerTC;
         tc = checkerTC;
@@ -133,33 +123,35 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
 
     itb = p->itb;
     dtb = p->dtb;
-#if FULL_SYSTEM
-    // Setup thread state stuff.
-    thread.cpu = this;
-    thread.setTid(0);
-
-    thread.quiesceEvent = new EndQuiesceEvent(tc);
-
-    system = p->system;
-    physmem = p->system->physmem;
-
-    if (p->profile) {
-        thread.profile = new FunctionProfile(p->system->kernelSymtab);
-        // @todo: This might be better as an ThreadContext instead of OzoneTC
-        Callback *cb =
-            new MakeCallback<OzoneTC,
-            &OzoneTC::dumpFuncProfile>(&ozoneTC);
-        registerExitCallback(cb);
-    }
 
-    // let's fill with a dummy node for now so we don't get a segfault
-    // on the first cycle when there's no node available.
-    static ProfileNode dummyNode;
-    thread.profileNode = &dummyNode;
-    thread.profilePC = 3;
-#else
-    thread.cpu = this;
-#endif // !FULL_SYSTEM
+    if (FullSystem) {
+        // Setup thread state stuff.
+        thread.cpu = this;
+        thread.setTid(0);
+
+        thread.quiesceEvent = new EndQuiesceEvent(tc);
+
+        system = p->system;
+        physmem = p->system->physmem;
+
+        if (p->profile) {
+            thread.profile = new FunctionProfile(p->system->kernelSymtab);
+            // @todo: This might be better as an ThreadContext instead of
+            // OzoneTC
+            Callback *cb =
+                new MakeCallback<OzoneTC,
+                &OzoneTC::dumpFuncProfile>(&ozoneTC);
+            registerExitCallback(cb);
+        }
+
+        // let's fill with a dummy node for now so we don't get a segfault
+        // on the first cycle when there's no node available.
+        static ProfileNode dummyNode;
+        thread.profileNode = &dummyNode;
+        thread.profilePC = 3;
+    } else {
+        thread.cpu = this;
+    }
 
     numInst = 0;
     startNumInst = 0;
@@ -194,25 +186,25 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
     frontEnd->renameTable.copyFrom(thread.renameTable);
     backEnd->renameTable.copyFrom(thread.renameTable);
 
-#if FULL_SYSTEM
-    Port *mem_port;
-    FunctionalPort *phys_port;
-    VirtualPort *virt_port;
-    phys_port = new FunctionalPort(csprintf("%s-%d-funcport",
-                                            name(), 0));
-    mem_port = system->physmem->getPort("functional");
-    mem_port->setPeer(phys_port);
-    phys_port->setPeer(mem_port);
-
-    virt_port = new VirtualPort(csprintf("%s-%d-vport",
-                                         name(), 0));
-    mem_port = system->physmem->getPort("functional");
-    mem_port->setPeer(virt_port);
-    virt_port->setPeer(mem_port);
-
-    thread.setPhysPort(phys_port);
-    thread.setVirtPort(virt_port);
-#endif
+    if (FullSystem) {
+        Port *mem_port;
+        FunctionalPort *phys_port;
+        VirtualPort *virt_port;
+        phys_port = new FunctionalPort(csprintf("%s-%d-funcport",
+                                                name(), 0));
+        mem_port = system->physmem->getPort("functional");
+        mem_port->setPeer(phys_port);
+        phys_port->setPeer(mem_port);
+
+        virt_port = new VirtualPort(csprintf("%s-%d-vport",
+                                             name(), 0));
+        mem_port = system->physmem->getPort("functional");
+        mem_port->setPeer(virt_port);
+        virt_port->setPeer(mem_port);
+
+        thread.setPhysPort(phys_port);
+        thread.setVirtPort(virt_port);
+    }
 
     DPRINTF(OzoneCPU, "OzoneCPU: Created Ozone cpu object.\n");
 }
@@ -321,10 +313,8 @@ OzoneCPU<Impl>::activateContext(int thread_num, int delay)
     notIdleFraction++;
     scheduleTickEvent(delay);
     _status = Running;
-#if FULL_SYSTEM
     if (thread.quiesceEvent && thread.quiesceEvent->scheduled())
         thread.quiesceEvent->deschedule();
-#endif
     thread.setStatus(ThreadContext::Active);
     frontEnd->wakeFromQuiesce();
 }
@@ -414,14 +404,14 @@ OzoneCPU<Impl>::init()
 
     // Mark this as in syscall so it won't need to squash
     thread.inSyscall = true;
-#if FULL_SYSTEM
-    for (int i = 0; i < threadContexts.size(); ++i) {
-        ThreadContext *tc = threadContexts[i];
+    if (FullSystem) {
+        for (int i = 0; i < threadContexts.size(); ++i) {
+            ThreadContext *tc = threadContexts[i];
 
-        // initialize CPU, including PC
-        TheISA::initCPU(tc, tc->contextId());
+            // initialize CPU, including PC
+            TheISA::initCPU(tc, tc->contextId());
+        }
     }
-#endif
     frontEnd->renameTable.copyFrom(thread.renameTable);
     backEnd->renameTable.copyFrom(thread.renameTable);
 
@@ -480,29 +470,24 @@ OzoneCPU<Impl>::unserialize(Checkpoint *cp, const std::string &section)
     thread.getTC()->copyArchRegs(temp.getTC());
 }
 
-#if FULL_SYSTEM
 template <class Impl>
 Addr
 OzoneCPU<Impl>::dbg_vtophys(Addr addr)
 {
     return vtophys(tc, addr);
 }
-#endif // FULL_SYSTEM
 
-#if FULL_SYSTEM
 template <class Impl>
 void
 OzoneCPU<Impl>::wakeup()
 {
     if (_status == Idle) {
         DPRINTF(IPI,"Suspended Processor awoke\n");
-//      thread.activate();
         // Hack for now.  Otherwise might have to go through the tc, or
         // I need to figure out what's the right thing to call.
         activateContext(thread.threadId(), 1);
     }
 }
-#endif // FULL_SYSTEM
 
 /* start simulation, program loaded, processor precise state initialized */
 template <class Impl>
@@ -535,7 +520,6 @@ OzoneCPU<Impl>::squashFromTC()
     backEnd->generateTCEvent();
 }
 
-#if !FULL_SYSTEM
 template <class Impl>
 void
 OzoneCPU<Impl>::syscall(uint64_t &callnum)
@@ -558,7 +542,7 @@ OzoneCPU<Impl>::syscall(uint64_t &callnum)
     frontEnd->renameTable.copyFrom(thread.renameTable);
     backEnd->renameTable.copyFrom(thread.renameTable);
 }
-#else
+
 template <class Impl>
 Fault
 OzoneCPU<Impl>::hwrei()
@@ -616,7 +600,6 @@ OzoneCPU<Impl>::simPalCheck(int palFunc)
 
     return true;
 }
-#endif
 
 template <class Impl>
 BaseCPU *
@@ -655,23 +638,19 @@ OzoneCPU<Impl>::OzoneTC::halt()
     cpu->haltContext(thread->threadId());
 }
 
-#if FULL_SYSTEM
 template <class Impl>
 void
 OzoneCPU<Impl>::OzoneTC::dumpFuncProfile()
 {
     thread->dumpFuncProfile();
 }
-#endif
 
 template <class Impl>
 void
 OzoneCPU<Impl>::OzoneTC::takeOverFrom(ThreadContext *old_context)
 {
     // some things should already be set up
-#if FULL_SYSTEM
     assert(getSystemPtr() == old_context->getSystemPtr());
-#endif
     assert(getProcessPtr() == old_context->getProcessPtr());
 
     // copy over functional state
@@ -680,9 +659,7 @@ OzoneCPU<Impl>::OzoneTC::takeOverFrom(ThreadContext *old_context)
     setCpuId(old_context->cpuId());
     setContextId(old_context->contextId());
 
-#if !FULL_SYSTEM
     setFuncExeInst(old_context->readFuncExeInst());
-#else
     EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
     if (other_quiesce) {
         // Point the quiesce event's TC at this TC so that it wakes up
@@ -706,10 +683,10 @@ template <class Impl>
 void
 OzoneCPU<Impl>::OzoneTC::regStats(const std::string &name)
 {
-#if FULL_SYSTEM
-    thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
-    thread->kernelStats->regStats(name + ".kern");
-#endif
+    if (FullSystem) {
+        thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
+        thread->kernelStats->regStats(name + ".kern");
+    }
 }
 
 template <class Impl>
@@ -726,7 +703,6 @@ void
 OzoneCPU<Impl>::OzoneTC::unserialize(Checkpoint *cp, const std::string &section)
 { }
 
-#if FULL_SYSTEM
 template <class Impl>
 EndQuiesceEvent *
 OzoneCPU<Impl>::OzoneTC::getQuiesceEvent()
@@ -761,7 +737,6 @@ OzoneCPU<Impl>::OzoneTC::profileSample()
 {
     thread->profileSample();
 }
-#endif
 
 template <class Impl>
 int
@@ -796,9 +771,7 @@ OzoneCPU<Impl>::OzoneTC::copyArchRegs(ThreadContext *tc)
         thread->renameTable[fp_idx]->setIntResult(tc->readFloatRegBits(i));
     }
 
-#if !FULL_SYSTEM
     thread->funcExeInst = tc->readFuncExeInst();
-#endif
 
     // Need to copy the TC values into the current rename table,
     // copy the misc regs.
diff --git a/src/cpu/ozone/dyn_inst.hh b/src/cpu/ozone/dyn_inst.hh
index c1853b1ed..3cce034c9 100644
--- a/src/cpu/ozone/dyn_inst.hh
+++ b/src/cpu/ozone/dyn_inst.hh
@@ -214,13 +214,10 @@ class OzoneDynInst : public BaseDynInst<Impl>
 
     void setMiscReg(int misc_reg, const MiscReg &val);
 
-#if FULL_SYSTEM
     Fault hwrei();
     void trap(Fault fault);
     bool simPalCheck(int palFunc);
-#else
     void syscall(uint64_t &callnum);
-#endif
 
     ListIt iqIt;
     bool iqItValid;
diff --git a/src/cpu/ozone/dyn_inst_impl.hh b/src/cpu/ozone/dyn_inst_impl.hh
index 5eb8ea8da..715c988fc 100644
--- a/src/cpu/ozone/dyn_inst_impl.hh
+++ b/src/cpu/ozone/dyn_inst_impl.hh
@@ -31,11 +31,8 @@
 #include "config/full_system.hh"
 #include "config/the_isa.hh"
 #include "cpu/ozone/dyn_inst.hh"
-#include "sim/faults.hh"
-
-#if FULL_SYSTEM
 #include "kern/kernel_stats.hh"
-#endif
+#include "sim/faults.hh"
 
 template <class Impl>
 OzoneDynInst<Impl>::OzoneDynInst(OzoneCPU *cpu)
@@ -239,8 +236,6 @@ OzoneDynInst<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
     this->thread->setMiscReg(misc_reg, val);
 }
 
-#if FULL_SYSTEM
-
 template <class Impl>
 Fault
 OzoneDynInst<Impl>::hwrei()
@@ -269,11 +264,10 @@ OzoneDynInst<Impl>::simPalCheck(int palFunc)
 {
     return this->cpu->simPalCheck(palFunc);
 }
-#else
+
 template <class Impl>
 void
 OzoneDynInst<Impl>::syscall(uint64_t &callnum)
 {
     this->cpu->syscall(callnum);
 }
-#endif
diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh
index 5d8919d4e..88576de3d 100644
--- a/src/cpu/ozone/front_end_impl.hh
+++ b/src/cpu/ozone/front_end_impl.hh
@@ -430,13 +430,10 @@ FrontEnd<Impl>::tick()
         numInstsReady[0]++;
         ++num_inst;
 
-#if FULL_SYSTEM
         if (inst->isQuiesce()) {
-//            warn("%lli: Quiesce instruction encountered, halting fetch!", curTick());
             status = QuiescePending;
             break;
         }
-#endif
 
         if (inst->predTaken()) {
             // Start over with tick?
@@ -984,9 +981,6 @@ FrontEnd<Impl>::takeOverFrom(ThreadContext *old_tc)
 
     cacheBlkValid = false;
 
-#if !FULL_SYSTEM
-//    pTable = params->pTable;
-#endif
     fetchFault = NoFault;
     serializeNext = false;
     barrierInst = NULL;
diff --git a/src/cpu/ozone/inorder_back_end.hh b/src/cpu/ozone/inorder_back_end.hh
index 5c2f9c28f..820e7d33b 100644
--- a/src/cpu/ozone/inorder_back_end.hh
+++ b/src/cpu/ozone/inorder_back_end.hh
@@ -73,9 +73,7 @@ class InorderBackEnd
 
     void regStats() { }
 
-#if FULL_SYSTEM
     void checkInterrupts();
-#endif
 
     void tick();
     void executeInsts();
diff --git a/src/cpu/ozone/inorder_back_end_impl.hh b/src/cpu/ozone/inorder_back_end_impl.hh
index 13c066fd2..59d1dab0d 100644
--- a/src/cpu/ozone/inorder_back_end_impl.hh
+++ b/src/cpu/ozone/inorder_back_end_impl.hh
@@ -79,7 +79,6 @@ InorderBackEnd<Impl>::setThreadState(OzoneThreadState<Impl> *thread_ptr)
     thread->setFuncExeInst(0);
 }
 
-#if FULL_SYSTEM
 template <class Impl>
 void
 InorderBackEnd<Impl>::checkInterrupts()
@@ -134,7 +133,6 @@ InorderBackEnd<Impl>::checkInterrupts()
         setSquashInfoFromXC();
     }
 }
-#endif
 
 template <class Impl>
 void
@@ -149,8 +147,7 @@ InorderBackEnd<Impl>::tick()
 
     // if (interrupt) then set thread PC, stall front end, record that
     // I'm waiting for it to drain.  (for now just squash)
-#if FULL_SYSTEM
-    if (interruptBlocked || cpu->checkInterrupts(tc)) {
+    if (FullSystem && (interruptBlocked || cpu->checkInterrupts(tc))) {
         if (!robEmpty()) {
             interruptBlocked = true;
         //AlphaDep
@@ -165,7 +162,6 @@ InorderBackEnd<Impl>::tick()
             return;
         }
     }
-#endif
 
     if (status != DcacheMissLoadStall &&
         status != DcacheMissStoreStall) {
@@ -180,15 +176,11 @@ InorderBackEnd<Impl>::tick()
             (*instsAdded)++;
         }
 
-#if FULL_SYSTEM
         if (faultFromFetch && robEmpty() && frontEnd->isEmpty()) {
             handleFault();
         } else {
             executeInsts();
         }
-#else
-        executeInsts();
-#endif
     }
 }
 
@@ -209,24 +201,24 @@ InorderBackEnd<Impl>::executeInsts()
         thread->setPC(commitPC);
         thread->setNextPC(inst->readNextPC());
 
-#if FULL_SYSTEM
-        int count = 0;
-        Addr oldpc;
-        do {
-            if (count == 0)
-                assert(!thread->inSyscall && !thread->trapPending);
-            oldpc = thread->readPC();
-            cpu->system->pcEventQueue.service(
-                thread->getXCProxy());
-            count++;
-        } while (oldpc != thread->readPC());
-        if (count > 1) {
-            DPRINTF(IBE, "PC skip function event, stopping commit\n");
-            completed_last_inst = false;
-            squashPending = true;
-            break;
+        if (FullSystem) {
+            int count = 0;
+            Addr oldpc;
+            do {
+                if (count == 0)
+                    assert(!thread->inSyscall && !thread->trapPending);
+                oldpc = thread->readPC();
+                cpu->system->pcEventQueue.service(
+                    thread->getXCProxy());
+                count++;
+            } while (oldpc != thread->readPC());
+            if (count > 1) {
+                DPRINTF(IBE, "PC skip function event, stopping commit\n");
+                completed_last_inst = false;
+                squashPending = true;
+                break;
+            }
         }
-#endif
 
         Fault inst_fault = NoFault;
 
@@ -296,7 +288,6 @@ InorderBackEnd<Impl>::executeInsts()
         }
 
         if (inst_fault != NoFault) {
-#if FULL_SYSTEM
             DPRINTF(IBE, "Inst [sn:%lli] PC %#x has a fault\n",
                     inst->seqNum, inst->readPC());
 
@@ -313,14 +304,8 @@ InorderBackEnd<Impl>::executeInsts()
 
             squashPending = true;
 
-            // Generate trap squash event.
-//            generateTrapEvent(tid);
             completed_last_inst = false;
             break;
-#else // !FULL_SYSTEM
-            panic("fault (%d) detected @ PC %08p", inst_fault,
-                  inst->PC);
-#endif // FULL_SYSTEM
         }
 
         for (int i = 0; i < inst->numDestRegs(); ++i) {
diff --git a/src/cpu/ozone/lw_back_end_impl.hh b/src/cpu/ozone/lw_back_end_impl.hh
index 880d0d183..c06a58754 100644
--- a/src/cpu/ozone/lw_back_end_impl.hh
+++ b/src/cpu/ozone/lw_back_end_impl.hh
@@ -520,7 +520,6 @@ LWBackEnd<Impl>::setCommBuffer(TimeBuffer<CommStruct> *_comm)
     fromCommit = comm->getWire(-1);
 }
 
-#if FULL_SYSTEM
 template <class Impl>
 void
 LWBackEnd<Impl>::checkInterrupts()
@@ -557,7 +556,6 @@ LWBackEnd<Impl>::checkInterrupts()
         }
     }
 }
-#endif
 
 template <class Impl>
 void
@@ -604,9 +602,7 @@ LWBackEnd<Impl>::tick()
 
     wbCycle = 0;
 
-#if FULL_SYSTEM
     checkInterrupts();
-#endif
 
     if (trapSquash) {
         assert(!tcSquash);
@@ -1049,16 +1045,8 @@ LWBackEnd<Impl>::commitInst(int inst_num)
             (inst->isStoreConditional() && inst->getFault() == NoFault) ||
             inst->isMemBarrier() ||
             inst->isWriteBarrier()) {
-#if !FULL_SYSTEM
-            // Hack to make sure syscalls aren't executed until all stores
-            // write back their data.  This direct communication shouldn't
-            // be used for anything other than this.
-            if (inst_num > 0 || LSQ.hasStoresToWB())
-#else
             if ((inst->isMemBarrier() || inst->isWriteBarrier() ||
-                    inst->isQuiesce()) &&
-                LSQ.hasStoresToWB())
-#endif
+                    inst->isQuiesce()) && LSQ.hasStoresToWB())
             {
                 DPRINTF(BE, "Waiting for all stores to writeback.\n");
                 return false;
@@ -1184,11 +1172,7 @@ LWBackEnd<Impl>::commitInst(int inst_num)
         ++freed_regs;
     }
 
-#if FULL_SYSTEM
-    if (thread->profile) {
-//        bool usermode =
-//            (xc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
-//        thread->profilePC = usermode ? 1 : inst->readPC();
+    if (FullSystem && thread->profile) {
         thread->profilePC = inst->readPC();
         ProfileNode *node = thread->profile->consume(thread->getTC(),
                                                      inst->staticInst);
@@ -1196,7 +1180,6 @@ LWBackEnd<Impl>::commitInst(int inst_num)
         if (node)
             thread->profileNode = node;
     }
-#endif
 
     if (inst->traceData) {
         inst->traceData->setFetchSeq(inst->seqNum);
@@ -1225,23 +1208,23 @@ LWBackEnd<Impl>::commitInst(int inst_num)
     toIEW->doneSeqNum = inst->seqNum;
     lastCommitCycle = curTick();
 
-#if FULL_SYSTEM
-    int count = 0;
-    Addr oldpc;
-    do {
-        if (count == 0)
-            assert(!thread->inSyscall && !thread->trapPending);
-        oldpc = thread->readPC();
-        cpu->system->pcEventQueue.service(
-            thread->getTC());
-        count++;
-    } while (oldpc != thread->readPC());
-    if (count > 1) {
-        DPRINTF(BE, "PC skip function event, stopping commit\n");
-        tcSquash = true;
-        return false;
+    if (FullSystem) {
+        int count = 0;
+        Addr oldpc;
+        do {
+            if (count == 0)
+                assert(!thread->inSyscall && !thread->trapPending);
+            oldpc = thread->readPC();
+            cpu->system->pcEventQueue.service(
+                thread->getTC());
+            count++;
+        } while (oldpc != thread->readPC());
+        if (count > 1) {
+            DPRINTF(BE, "PC skip function event, stopping commit\n");
+            tcSquash = true;
+            return false;
+        }
     }
-#endif
     return true;
 }
 
diff --git a/src/cpu/ozone/simple_cpu_builder.cc b/src/cpu/ozone/simple_cpu_builder.cc
index f4446ede3..512dc3b9e 100644
--- a/src/cpu/ozone/simple_cpu_builder.cc
+++ b/src/cpu/ozone/simple_cpu_builder.cc
@@ -60,21 +60,20 @@ SimpleOzoneCPUParams::create()
 {
     SimpleOzoneCPU *cpu;
 
-#if FULL_SYSTEM
-    // Full-system only supports a single thread for the moment.
-    ThreadID actual_num_threads = 1;
-#else
-    // In non-full-system mode, we infer the number of threads from
-    // the workload if it's not explicitly specified.
-    ThreadID actual_num_threads =
-        numThreads.isValid() ? numThreads : workload.size();
-
-    if (workload.size() == 0) {
-        fatal("Must specify at least one workload!");
+    if (FullSystem) {
+        // Full-system only supports a single thread for the moment.
+        ThreadID actual_num_threads = 1;
+    } else {
+        // In non-full-system mode, we infer the number of threads from
+        // the workload if it's not explicitly specified.
+        ThreadID actual_num_threads =
+            numThreads.isValid() ? numThreads : workload.size();
+
+        if (workload.size() == 0) {
+            fatal("Must specify at least one workload!");
+        }
     }
 
-#endif
-
     SimpleParams *params = new SimpleParams;
 
     params->clock = clock;
@@ -87,10 +86,7 @@ SimpleOzoneCPUParams::create()
 
     params->system = system;
     params->cpu_id = cpu_id;
-#if !FULL_SYSTEM
     params->workload = workload;
-//    params->pTable = page_table;
-#endif // FULL_SYSTEM
 
     params->mem = mem;
     params->checker = checker;
diff --git a/src/cpu/ozone/simple_params.hh b/src/cpu/ozone/simple_params.hh
index b241dea73..228b78128 100644
--- a/src/cpu/ozone/simple_params.hh
+++ b/src/cpu/ozone/simple_params.hh
@@ -56,9 +56,7 @@ class SimpleParams : public BaseCPU::Params
   public:
 
     TheISA::TLB *itb; TheISA::TLB *dtb;
-#if !FULL_SYSTEM
     std::vector<Process *> workload;
-#endif // FULL_SYSTEM
 
     //Page Table
     PageTable *pTable;
diff --git a/src/cpu/ozone/thread_state.hh b/src/cpu/ozone/thread_state.hh
index 638b9d86c..98ecd850c 100644
--- a/src/cpu/ozone/thread_state.hh
+++ b/src/cpu/ozone/thread_state.hh
@@ -45,14 +45,11 @@
 class Event;
 //class Process;
 
-#if FULL_SYSTEM
 class EndQuiesceEvent;
+class FunctionalMemory;
 class FunctionProfile;
-class ProfileNode;
-#else
 class Process;
-class FunctionalMemory;
-#endif
+class ProfileNode;
 
 // Maybe this ozone thread state should only really have committed state?
 // I need to think about why I'm using this and what it's useful for.  Clearly
@@ -66,7 +63,6 @@ struct OzoneThreadState : public ThreadState {
     typedef typename Impl::CPUType CPUType;
     typedef TheISA::MiscReg MiscReg;
 
-#if FULL_SYSTEM
     OzoneThreadState(CPUType *_cpu, int _thread_num)
         : ThreadState(_cpu, -1, _thread_num),
           intrflag(0), cpu(_cpu), inSyscall(0), trapPending(0)
@@ -86,14 +82,13 @@ struct OzoneThreadState : public ThreadState {
         profilePC = 3;
         miscRegFile.clear();
     }
-#else
+
     OzoneThreadState(CPUType *_cpu, int _thread_num, Process *_process)
         : ThreadState(_cpu, -1, _thread_num, _process),
           cpu(_cpu), inSyscall(0), trapPending(0)
     {
         miscRegFile.clear();
     }
-#endif
 
     RenameTable<Impl> renameTable;
 
@@ -147,13 +142,11 @@ struct OzoneThreadState : public ThreadState {
     void setNextPC(uint64_t val)
     { nextPC = val; }
 
-#if FULL_SYSTEM
     void dumpFuncProfile()
     {
         std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name()));
         profile->dump(tc, *os);
     }
-#endif
 };
 
 #endif // __CPU_OZONE_THREAD_STATE_HH__
diff --git a/src/cpu/pc_event.cc b/src/cpu/pc_event.cc
index f9955d014..a07d787f0 100644
--- a/src/cpu/pc_event.cc
+++ b/src/cpu/pc_event.cc
@@ -36,7 +36,6 @@
 
 #include "base/debug.hh"
 #include "base/trace.hh"
-#include "config/full_system.hh"
 #include "cpu/base.hh"
 #include "cpu/pc_event.hh"
 #include "cpu/thread_context.hh"
@@ -138,7 +137,6 @@ BreakPCEvent::process(ThreadContext *tc)
         delete this;
 }
 
-#if FULL_SYSTEM
 void
 sched_break_pc_sys(System *sys, Addr addr)
 {
@@ -154,4 +152,3 @@ sched_break_pc(Addr addr)
     }
 
 }
-#endif
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 9995ed55e..fed94ffd8 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -87,11 +87,9 @@ AtomicSimpleCPU::init()
     if (FullSystem) {
         ThreadID size = threadContexts.size();
         for (ThreadID i = 0; i < size; ++i) {
-#if FULL_SYSTEM
             ThreadContext *tc = threadContexts[i];
             // initialize CPU, including PC
             TheISA::initCPU(tc, tc->contextId());
-#endif
         }
     }
     if (hasPhysMemPort) {
@@ -618,9 +616,7 @@ AtomicSimpleCPU *
 AtomicSimpleCPUParams::create()
 {
     numThreads = 1;
-#if !FULL_SYSTEM
     if (!FullSystem && workload.size() != 1)
         panic("only one workload allowed");
-#endif
     return new AtomicSimpleCPU(this);
 }
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index e4940a55f..610cc6b89 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -73,6 +73,7 @@
 #include "params/BaseSimpleCPU.hh"
 #include "sim/byteswap.hh"
 #include "sim/debug.hh"
+#include "sim/full_system.hh"
 #include "sim/sim_events.hh"
 #include "sim/sim_object.hh"
 #include "sim/stats.hh"
@@ -84,12 +85,11 @@ using namespace TheISA;
 BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
     : BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL)
 {
-#if FULL_SYSTEM
-    thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
-#else
-    thread = new SimpleThread(this, /* thread_num */ 0, p->workload[0],
-            p->itb, p->dtb);
-#endif // !FULL_SYSTEM
+    if (FullSystem)
+        thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
+    else
+        thread = new SimpleThread(this, /* thread_num */ 0, p->workload[0],
+                p->itb, p->dtb);
 
     thread->setStatus(ThreadContext::Halted);
 
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index cd640da31..983672c27 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -77,11 +77,9 @@ TimingSimpleCPU::init()
     BaseCPU::init();
     if (FullSystem) {
         for (int i = 0; i < threadContexts.size(); ++i) {
-#if FULL_SYSTEM
             ThreadContext *tc = threadContexts[i];
             // initialize CPU, including PC
             TheISA::initCPU(tc, _cpuId);
-#endif
         }
     }
 }
@@ -1009,9 +1007,7 @@ TimingSimpleCPU *
 TimingSimpleCPUParams::create()
 {
     numThreads = 1;
-#if !FULL_SYSTEM
     if (!FullSystem && workload.size() != 1)
         panic("only one workload allowed");
-#endif
     return new TimingSimpleCPU(this);
 }
diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index f2d0fde30..edde884e7 100644
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -50,6 +50,7 @@
 #include "mem/translating_port.hh"
 #include "mem/vport.hh"
 #include "params/BaseCPU.hh"
+#include "sim/full_system.hh"
 #include "sim/process.hh"
 #include "sim/serialize.hh"
 #include "sim/sim_exit.hh"
@@ -58,7 +59,6 @@
 using namespace std;
 
 // constructor
-#if !FULL_SYSTEM
 SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
                            TheISA::TLB *_itb, TheISA::TLB *_dtb)
     : ThreadState(_cpu, _thread_num, _process),
@@ -67,7 +67,6 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
     clearArchRegs();
     tc = new ProxyThreadContext<SimpleThread>(this);
 }
-#else
 SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
                            TheISA::TLB *_itb, TheISA::TLB *_dtb,
                            bool use_kernel_stats)
@@ -98,7 +97,6 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
     if (use_kernel_stats)
         kernelStats = new TheISA::Kernel::Statistics(system);
 }
-#endif
 
 SimpleThread::SimpleThread()
     : ThreadState(NULL, -1, NULL)
@@ -117,28 +115,27 @@ void
 SimpleThread::takeOverFrom(ThreadContext *oldContext)
 {
     // some things should already be set up
-#if FULL_SYSTEM
-    assert(system == oldContext->getSystemPtr());
-#endif
+    if (FullSystem)
+        assert(system == oldContext->getSystemPtr());
     assert(process == oldContext->getProcessPtr());
 
     copyState(oldContext);
-#if FULL_SYSTEM
-    EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent();
-    if (quiesce) {
-        // Point the quiesce event's TC at this TC so that it wakes up
-        // the proper CPU.
-        quiesce->tc = tc;
+    if (FullSystem) {
+        EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent();
+        if (quiesce) {
+            // Point the quiesce event's TC at this TC so that it wakes up
+            // the proper CPU.
+            quiesce->tc = tc;
+        }
+        if (quiesceEvent) {
+            quiesceEvent->tc = tc;
+        }
+
+        TheISA::Kernel::Statistics *stats = oldContext->getKernelStats();
+        if (stats) {
+            kernelStats = stats;
+        }
     }
-    if (quiesceEvent) {
-        quiesceEvent->tc = tc;
-    }
-
-    TheISA::Kernel::Statistics *stats = oldContext->getKernelStats();
-    if (stats) {
-        kernelStats = stats;
-    }
-#endif
 
     storeCondFailures = 0;
 
@@ -150,16 +147,16 @@ SimpleThread::copyTC(ThreadContext *context)
 {
     copyState(context);
 
-#if FULL_SYSTEM
-    EndQuiesceEvent *quiesce = context->getQuiesceEvent();
-    if (quiesce) {
-        quiesceEvent = quiesce;
-    }
-    TheISA::Kernel::Statistics *stats = context->getKernelStats();
-    if (stats) {
-        kernelStats = stats;
+    if (FullSystem) {
+        EndQuiesceEvent *quiesce = context->getQuiesceEvent();
+        if (quiesce) {
+            quiesceEvent = quiesce;
+        }
+        TheISA::Kernel::Statistics *stats = context->getKernelStats();
+        if (stats) {
+            kernelStats = stats;
+        }
     }
-#endif
 }
 
 void
@@ -168,9 +165,8 @@ SimpleThread::copyState(ThreadContext *oldContext)
     // copy over functional state
     _status = oldContext->status();
     copyArchRegs(oldContext);
-#if !FULL_SYSTEM
-    funcExeInst = oldContext->readFuncExeInst();
-#endif
+    if (FullSystem)
+        funcExeInst = oldContext->readFuncExeInst();
 
     _threadId = oldContext->threadId();
     _contextId = oldContext->contextId();
@@ -241,15 +237,6 @@ SimpleThread::suspend()
 
     lastActivate = curTick();
     lastSuspend = curTick();
-/*
-#if FULL_SYSTEM
-    // Don't change the status from active if there are pending interrupts
-    if (cpu->checkInterrupts()) {
-        assert(status() == ThreadContext::Active);
-        return;
-    }
-#endif
-*/
     _status = ThreadContext::Suspended;
     cpu->suspendContext(_threadId);
 }
@@ -269,10 +256,8 @@ SimpleThread::halt()
 void
 SimpleThread::regStats(const string &name)
 {
-#if FULL_SYSTEM
-    if (kernelStats)
+    if (FullSystem && kernelStats)
         kernelStats->regStats(name + ".kern");
-#endif
 }
 
 void
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 817fdf8ef..2180b13a0 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -126,14 +126,13 @@ class SimpleThread : public ThreadState
     Decoder decoder;
 
     // constructor: initialize SimpleThread from given process structure
-#if FULL_SYSTEM
+    // FS
     SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
                  TheISA::TLB *_itb, TheISA::TLB *_dtb,
                  bool use_kernel_stats = true);
-#else
+    // SE
     SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
                  TheISA::TLB *_itb, TheISA::TLB *_dtb);
-#endif
 
     SimpleThread();
 
diff --git a/src/cpu/thread_state.cc b/src/cpu/thread_state.cc
index efb1d5469..ef81271a8 100644
--- a/src/cpu/thread_state.cc
+++ b/src/cpu/thread_state.cc
@@ -28,29 +28,24 @@
  * Authors: Kevin Lim
  */
 
+#include "arch/kernel_stats.hh"
 #include "base/output.hh"
 #include "cpu/base.hh"
 #include "cpu/profile.hh"
+#include "cpu/quiesce_event.hh"
 #include "cpu/thread_state.hh"
 #include "mem/port.hh"
 #include "mem/translating_port.hh"
 #include "mem/vport.hh"
+#include "sim/full_system.hh"
 #include "sim/serialize.hh"
 
-#if FULL_SYSTEM
-#include "arch/kernel_stats.hh"
-#include "cpu/quiesce_event.hh"
-#endif
-
 ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process)
     : numInst(0), numLoad(0), _status(ThreadContext::Halted),
       baseCpu(cpu), _threadId(_tid), lastActivate(0), lastSuspend(0),
-#if FULL_SYSTEM
       profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL),
-      kernelStats(NULL),
-#endif
-      process(_process), port(NULL), virtPort(NULL), physPort(NULL),
-      funcExeInst(0), storeCondFailures(0)
+      kernelStats(NULL), process(_process), port(NULL), virtPort(NULL),
+      physPort(NULL), funcExeInst(0), storeCondFailures(0)
 {
 }
 
@@ -69,14 +64,14 @@ ThreadState::serialize(std::ostream &os)
     // thread_num and cpu_id are deterministic from the config
     SERIALIZE_SCALAR(funcExeInst);
 
-#if FULL_SYSTEM
-    Tick quiesceEndTick = 0;
-    if (quiesceEvent->scheduled())
-        quiesceEndTick = quiesceEvent->when();
-    SERIALIZE_SCALAR(quiesceEndTick);
-    if (kernelStats)
-        kernelStats->serialize(os);
-#endif
+    if (FullSystem) {
+        Tick quiesceEndTick = 0;
+        if (quiesceEvent->scheduled())
+            quiesceEndTick = quiesceEvent->when();
+        SERIALIZE_SCALAR(quiesceEndTick);
+        if (kernelStats)
+            kernelStats->serialize(os);
+    }
 }
 
 void
@@ -87,14 +82,14 @@ ThreadState::unserialize(Checkpoint *cp, const std::string &section)
     // thread_num and cpu_id are deterministic from the config
     UNSERIALIZE_SCALAR(funcExeInst);
 
-#if FULL_SYSTEM
-    Tick quiesceEndTick;
-    UNSERIALIZE_SCALAR(quiesceEndTick);
-    if (quiesceEndTick)
-        baseCpu->schedule(quiesceEvent, quiesceEndTick);
-    if (kernelStats)
-        kernelStats->unserialize(cp, section);
-#endif
+    if (FullSystem) {
+        Tick quiesceEndTick;
+        UNSERIALIZE_SCALAR(quiesceEndTick);
+        if (quiesceEndTick)
+            baseCpu->schedule(quiesceEvent, quiesceEndTick);
+        if (kernelStats)
+            kernelStats->unserialize(cp, section);
+    }
 }
 
 void