request: rename INST_READ to INST_FETCH.

4 files changed, 9 insertions, 8 deletions

diff --git a/src/cpu/ozone/inorder_back_end.hh b/src/cpu/ozone/inorder_back_end.hh
index 96f3a901f..dd9e23f97 100644
--- a/src/cpu/ozone/inorder_back_end.hh
+++ b/src/cpu/ozone/inorder_back_end.hh
@@ -211,7 +211,7 @@ InorderBackEnd<Impl>::read(Addr addr, T &data, unsigned flags)
         memReq->cmd = Read;
         memReq->completionEvent = NULL;
         memReq->time = curTick;
-        memReq->flags &= ~INST_READ;
+        memReq->flags &= ~INST_FETCH;
         MemAccessResult result = dcacheInterface->access(memReq);
 
         // Ugly hack to get an event scheduled *only* if the access is
@@ -252,7 +252,7 @@ InorderBackEnd<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
 //      memcpy(memReq->data,(uint8_t *)&data,memReq->size);
         memReq->completionEvent = NULL;
         memReq->time = curTick;
-        memReq->flags &= ~INST_READ;
+        memReq->flags &= ~INST_FETCH;
         MemAccessResult result = dcacheInterface->access(memReq);
 
         // Ugly hack to get an event scheduled *only* if the access is
@@ -293,7 +293,7 @@ InorderBackEnd<Impl>::read(MemReqPtr &req, T &data, int load_idx)
     req->time = curTick;
     assert(!req->data);
     req->data = new uint8_t[64];
-    req->flags &= ~INST_READ;
+    req->flags &= ~INST_FETCH;
     Fault fault = cpu->read(req, data);
     memcpy(req->data, &data, sizeof(T));
 
@@ -363,7 +363,7 @@ InorderBackEnd<Impl>::write(MemReqPtr &req, T &data, int store_idx)
         memcpy(req->data,(uint8_t *)&data,req->size);
         req->completionEvent = NULL;
         req->time = curTick;
-        req->flags &= ~INST_READ;
+        req->flags &= ~INST_FETCH;
         MemAccessResult result = dcacheInterface->access(req);
 
         // Ugly hack to get an event scheduled *only* if the access is
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 71d26f828..5058db0da 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -48,6 +48,7 @@
 #include "cpu/static_inst.hh"
 #include "cpu/thread_context.hh"
 #include "mem/packet.hh"
+#include "mem/request.hh"
 #include "sim/byteswap.hh"
 #include "sim/debug.hh"
 #include "sim/host.hh"
@@ -280,7 +281,7 @@ BaseSimpleCPU::copy(Addr dest)
             memReq->dest = dest_addr;
             memReq->size = 64;
             memReq->time = curTick;
-            memReq->flags &= ~INST_READ;
+            memReq->flags &= ~INST_FETCH;
             dcacheInterface->access(memReq);
         }
     }
@@ -346,7 +347,7 @@ BaseSimpleCPU::setupFetchRequest(Request *req)
 #endif
 
     Addr fetchPC = (threadPC & PCMask) + fetchOffset;
-    req->setVirt(0, fetchPC, sizeof(MachInst), 0, threadPC);
+    req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, threadPC);
 }
 
 
diff --git a/src/cpu/trace/reader/itx_reader.cc b/src/cpu/trace/reader/itx_reader.cc
index f27b82ff1..e03ac6905 100644
--- a/src/cpu/trace/reader/itx_reader.cc
+++ b/src/cpu/trace/reader/itx_reader.cc
@@ -168,7 +168,7 @@ ITXReader::getNextReq(MemReqPtr &req)
                     break;
                   case ITXCode:
                     tmp_req->cmd = Read;
-                    tmp_req->flags |= INST_READ;
+                    tmp_req->flags |= INST_FETCH;
                     break;
                   default:
                     fatal("Unknown ITX type");
diff --git a/src/cpu/trace/trace_cpu.cc b/src/cpu/trace/trace_cpu.cc
index ab00b3093..b286f1e40 100644
--- a/src/cpu/trace/trace_cpu.cc
+++ b/src/cpu/trace/trace_cpu.cc
@@ -68,7 +68,7 @@ TraceCPU::tick()
 
     while (nextReq && curTick >= nextCycle) {
         assert(nextReq->thread_num < 4 && "Not enough threads");
-        if (nextReq->isInstRead() && icacheInterface) {
+        if (nextReq->isInstFetch() && icacheInterface) {
             if (icacheInterface->isBlocked())
                 break;