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authorAndreas Sandberg <Andreas.Sandberg@ARM.com>2014-10-16 05:49:39 -0400
committerAndreas Sandberg <Andreas.Sandberg@ARM.com>2014-10-16 05:49:39 -0400
commit3697990c27243f0c454f2fab0f12ed06759c97b9 (patch)
treec7fe75d2cf328c26bc31cfe405d91afc2c4aa757 /src/cpu
parent132ea6319ab9292bef7c0ea87f396ef9de2db0fe (diff)
downloadgem5-3697990c27243f0c454f2fab0f12ed06759c97b9.tar.xz
arm: Add a model of an ARM PMUv3
This class implements a subset of the ARM PMU v3 specification as described in the ARMv8 reference manual. It supports most of the features of the PMU, however the following features are known to be missing: * Event filtering (e.g., from different privilege levels). * Access controls (the PMU currently ignores the execution level). * The chain counter (event no. 0x1E) is unimplemented. The PMU itself does not implement any events, it merely provides an interface for the configuration scripts to hook up probes that drive events. Configuration scripts should call addEventProbe() to configure custom events or high-level methods to configure architected events. The Python implementation of addEventProbe() automatically delays event type registration until after instantiation. In order to support CPU switching and some combined counters (e.g., memory references synthesized from loads and stores), the PMU allows multiple probes per event type. When creating a system that switches between CPU models that share the same PMU, PMU events for all of the CPU models can be registered with the PMU. Kudos to Matt Horsnell for the initial gem5 implementation of the PMU.
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