includes: sort includes again

21 files changed, 56 insertions, 62 deletions

diff --git a/src/cpu/exetrace.hh b/src/cpu/exetrace.hh
index a1bbe3735..aa0831dfd 100644
--- a/src/cpu/exetrace.hh
+++ b/src/cpu/exetrace.hh
@@ -29,14 +29,14 @@
  *          Nathan Binkert
  */
 
-#ifndef __EXETRACE_HH__
-#define __EXETRACE_HH__
+#ifndef __CPU_EXETRACE_HH__
+#define __CPU_EXETRACE_HH__
 
 #include "base/trace.hh"
-#include "cpu/static_inst.hh"
 #include "base/types.hh"
-#include "sim/insttracer.hh"
+#include "cpu/static_inst.hh"
 #include "params/ExeTracer.hh"
+#include "sim/insttracer.hh"
 
 class ThreadContext;
 
@@ -88,4 +88,4 @@ class ExeTracer : public InstTracer
 
 /* namespace Trace */ }
 
-#endif // __EXETRACE_HH__
+#endif // __CPU_EXETRACE_HH__
diff --git a/src/cpu/inorder/comm.hh b/src/cpu/inorder/comm.hh
index 1a7fc9050..f1b3cacac 100644
--- a/src/cpu/inorder/comm.hh
+++ b/src/cpu/inorder/comm.hh
@@ -36,10 +36,10 @@
 
 #include "arch/faults.hh"
 #include "arch/isa_traits.hh"
+#include "base/types.hh"
 #include "cpu/inorder/inorder_dyn_inst.hh"
 #include "cpu/inorder/pipeline_traits.hh"
 #include "cpu/inst_seq.hh"
-#include "base/types.hh"
 
 /** Struct that defines the information passed from in between stages */
 /** This information mainly goes forward through the pipeline. */
diff --git a/src/cpu/inorder/inorder_trace.hh b/src/cpu/inorder/inorder_trace.hh
index eb1287370..ccc868f15 100644
--- a/src/cpu/inorder/inorder_trace.hh
+++ b/src/cpu/inorder/inorder_trace.hh
@@ -29,19 +29,18 @@
  * Authors: Korey Sewell
  */
 
-#ifndef __INORDERTRACE_HH__
-#define __INORDERTRACE_HH__
+#ifndef __CPU_INORDER_INORDER_TRACE_HH__
+#define __CPU_INORDER_INORDER_TRACE_HH__
 
 #include "base/trace.hh"
-#include "cpu/static_inst.hh"
 #include "base/types.hh"
-#include "sim/insttracer.hh"
-#include "params/InOrderTrace.hh"
 #include "cpu/exetrace.hh"
+#include "cpu/static_inst.hh"
+#include "params/InOrderTrace.hh"
+#include "sim/insttracer.hh"
 
 class ThreadContext;
 
-
 namespace Trace {
 
 class InOrderTraceRecord : public ExeTracerRecord
@@ -95,4 +94,4 @@ class InOrderTrace : public InstTracer
 
 /* namespace Trace */ }
 
-#endif // __EXETRACE_HH__
+#endif // __CPU_INORDER_INORDER_TRACE_HH__
diff --git a/src/cpu/inteltrace.hh b/src/cpu/inteltrace.hh
index 56fafe93a..c4ace4f4b 100644
--- a/src/cpu/inteltrace.hh
+++ b/src/cpu/inteltrace.hh
@@ -29,18 +29,17 @@
  *          Nathan Binkert
  */
 
-#ifndef __INTELTRACE_HH__
-#define __INTELTRACE_HH__
+#ifndef __CPU_INTELTRACE_HH__
+#define __CPU_INTELTRACE_HH__
 
 #include "base/trace.hh"
+#include "base/types.hh"
 #include "cpu/static_inst.hh"
 #include "params/IntelTrace.hh"
-#include "base/types.hh"
 #include "sim/insttracer.hh"
 
 class ThreadContext;
 
-
 namespace Trace {
 
 class IntelTraceRecord : public InstRecord
@@ -85,4 +84,4 @@ class IntelTrace : public InstTracer
 
 /* namespace Trace */ }
 
-#endif // __EXETRACE_HH__
+#endif // __CPU_INTELTRACE_HH__
diff --git a/src/cpu/legiontrace.hh b/src/cpu/legiontrace.hh
index 19a996ed3..829941d4b 100644
--- a/src/cpu/legiontrace.hh
+++ b/src/cpu/legiontrace.hh
@@ -29,13 +29,13 @@
  *          Nathan Binkert
  */
 
-#ifndef __LEGIONTRACE_HH__
-#define __LEGIONTRACE_HH__
+#ifndef __CPU_LEGIONTRACE_HH__
+#define __CPU_LEGIONTRACE_HH__
 
 #include "base/trace.hh"
+#include "base/types.hh"
 #include "cpu/static_inst.hh"
 #include "params/LegionTrace.hh"
-#include "base/types.hh"
 #include "sim/insttracer.hh"
 
 class ThreadContext;
@@ -78,4 +78,4 @@ class LegionTrace : public InstTracer
 
 /* namespace Trace */ }
 
-#endif // __LEGIONTRACE_HH__
+#endif // __CPU_LEGIONTRACE_HH__
diff --git a/src/cpu/nativetrace.hh b/src/cpu/nativetrace.hh
index 12d96e0ae..f137e66ee 100644
--- a/src/cpu/nativetrace.hh
+++ b/src/cpu/nativetrace.hh
@@ -29,19 +29,18 @@
  *          Nathan Binkert
  */
 
-#ifndef __NATIVETRACE_HH__
-#define __NATIVETRACE_HH__
+#ifndef __CPU_NATIVETRACE_HH__
+#define __CPU_NATIVETRACE_HH__
 
+#include "arch/x86/floatregs.hh"
+#include "arch/x86/intregs.hh"
 #include "base/trace.hh"
-#include "cpu/static_inst.hh"
 #include "base/types.hh"
+#include "cpu/static_inst.hh"
 #include "sim/insttracer.hh"
-#include "arch/x86/intregs.hh"
-#include "arch/x86/floatregs.hh"
 
 class ThreadContext;
 
-
 namespace Trace {
 
 class NativeTrace;
@@ -213,4 +212,4 @@ class NativeTrace : public InstTracer
 
 /* namespace Trace */ }
 
-#endif // __EXETRACE_HH__
+#endif // __CPU_NATIVETRACE_HH__
diff --git a/src/cpu/o3/2bit_local_pred.hh b/src/cpu/o3/2bit_local_pred.hh
index 7669c6b97..8b7bb8463 100644
--- a/src/cpu/o3/2bit_local_pred.hh
+++ b/src/cpu/o3/2bit_local_pred.hh
@@ -31,11 +31,11 @@
 #ifndef __CPU_O3_2BIT_LOCAL_PRED_HH__
 #define __CPU_O3_2BIT_LOCAL_PRED_HH__
 
-#include "cpu/o3/sat_counter.hh"
-#include "base/types.hh"
-
 #include <vector>
 
+#include "base/types.hh"
+#include "cpu/o3/sat_counter.hh"
+
 /**
  * Implements a local predictor that uses the PC to index into a table of
  * counters.  Note that any time a pointer to the bp_history is given, it
diff --git a/src/cpu/o3/bpred_unit.hh b/src/cpu/o3/bpred_unit.hh
index 15d34316e..4875c03d8 100644
--- a/src/cpu/o3/bpred_unit.hh
+++ b/src/cpu/o3/bpred_unit.hh
@@ -31,18 +31,16 @@
 #ifndef __CPU_O3_BPRED_UNIT_HH__
 #define __CPU_O3_BPRED_UNIT_HH__
 
+#include <list>
+
 #include "base/statistics.hh"
+#include "base/types.hh"
 #include "cpu/inst_seq.hh"
-
 #include "cpu/o3/2bit_local_pred.hh"
 #include "cpu/o3/btb.hh"
 #include "cpu/o3/ras.hh"
 #include "cpu/o3/tournament_pred.hh"
 
-#include "base/types.hh"
-
-#include <list>
-
 class DerivO3CPUParams;
 
 /**
diff --git a/src/cpu/o3/comm.hh b/src/cpu/o3/comm.hh
index a486f340d..23b836f73 100644
--- a/src/cpu/o3/comm.hh
+++ b/src/cpu/o3/comm.hh
@@ -33,9 +33,9 @@
 
 #include <vector>
 
-#include "sim/faults.hh"
-#include "cpu/inst_seq.hh"
 #include "base/types.hh"
+#include "cpu/inst_seq.hh"
+#include "sim/faults.hh"
 
 // Typedef for physical register index type. Although the Impl would be the
 // most likely location for this, there are a few classes that need this
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 96a4aebef..4d8033a8c 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -32,17 +32,17 @@
 #include <algorithm>
 #include <cstring>
 
-#include "config/use_checker.hh"
-
 #include "arch/isa_traits.hh"
 #include "arch/utility.hh"
+#include "base/types.hh"
+#include "config/use_checker.hh"
 #include "cpu/checker/cpu.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/o3/fetch.hh"
 #include "mem/packet.hh"
 #include "mem/request.hh"
+#include "params/DerivO3CPU.hh"
 #include "sim/byteswap.hh"
-#include "base/types.hh"
 #include "sim/core.hh"
 
 #if FULL_SYSTEM
@@ -51,8 +51,6 @@
 #include "sim/system.hh"
 #endif // FULL_SYSTEM
 
-#include "params/DerivO3CPU.hh"
-
 template<class Impl>
 void
 DefaultFetch<Impl>::IcachePort::setPeer(Port *port)
diff --git a/src/cpu/o3/inst_queue.hh b/src/cpu/o3/inst_queue.hh
index 5537a57e7..0b814ccb4 100644
--- a/src/cpu/o3/inst_queue.hh
+++ b/src/cpu/o3/inst_queue.hh
@@ -38,11 +38,11 @@
 
 #include "base/statistics.hh"
 #include "base/timebuf.hh"
+#include "base/types.hh"
 #include "cpu/inst_seq.hh"
 #include "cpu/o3/dep_graph.hh"
 #include "cpu/op_class.hh"
 #include "sim/eventq.hh"
-#include "base/types.hh"
 
 class DerivO3CPUParams;
 class FUPool;
diff --git a/src/cpu/o3/ras.hh b/src/cpu/o3/ras.hh
index e9a52fd37..a36faf79a 100644
--- a/src/cpu/o3/ras.hh
+++ b/src/cpu/o3/ras.hh
@@ -31,9 +31,10 @@
 #ifndef __CPU_O3_RAS_HH__
 #define __CPU_O3_RAS_HH__
 
-#include "base/types.hh"
 #include <vector>
 
+#include "base/types.hh"
+
 /** Return address stack class, implements a simple RAS. */
 class ReturnAddrStack
 {
diff --git a/src/cpu/o3/store_set.hh b/src/cpu/o3/store_set.hh
index 88f5e0d07..57cd2a197 100644
--- a/src/cpu/o3/store_set.hh
+++ b/src/cpu/o3/store_set.hh
@@ -36,8 +36,8 @@
 #include <utility>
 #include <vector>
 
-#include "cpu/inst_seq.hh"
 #include "base/types.hh"
+#include "cpu/inst_seq.hh"
 
 struct ltseqnum {
     bool operator()(const InstSeqNum &lhs, const InstSeqNum &rhs) const
diff --git a/src/cpu/o3/tournament_pred.hh b/src/cpu/o3/tournament_pred.hh
index 31e539628..96bd43ed6 100644
--- a/src/cpu/o3/tournament_pred.hh
+++ b/src/cpu/o3/tournament_pred.hh
@@ -31,10 +31,11 @@
 #ifndef __CPU_O3_TOURNAMENT_PRED_HH__
 #define __CPU_O3_TOURNAMENT_PRED_HH__
 
-#include "cpu/o3/sat_counter.hh"
-#include "base/types.hh"
 #include <vector>
 
+#include "base/types.hh"
+#include "cpu/o3/sat_counter.hh"
+
 /**
  * Implements a tournament branch predictor, hopefully identical to the one
  * used in the 21264.  It has a local predictor, which uses a local history
diff --git a/src/cpu/ozone/ea_list.hh b/src/cpu/ozone/ea_list.hh
index eadd577a4..bf05884b5 100644
--- a/src/cpu/ozone/ea_list.hh
+++ b/src/cpu/ozone/ea_list.hh
@@ -35,8 +35,8 @@
 #include <list>
 #include <utility>
 
-#include "cpu/inst_seq.hh"
 #include "base/types.hh"
+#include "cpu/inst_seq.hh"
 
 /**
  * Simple class to hold onto a list of pairs, each pair having a memory
diff --git a/src/cpu/ozone/inst_queue.hh b/src/cpu/ozone/inst_queue.hh
index 8235760b4..5af916fb5 100644
--- a/src/cpu/ozone/inst_queue.hh
+++ b/src/cpu/ozone/inst_queue.hh
@@ -38,8 +38,8 @@
 
 #include "base/statistics.hh"
 #include "base/timebuf.hh"
-#include "cpu/inst_seq.hh"
 #include "base/types.hh"
+#include "cpu/inst_seq.hh"
 
 class FUPool;
 class MemInterface;
diff --git a/src/cpu/ozone/null_predictor.hh b/src/cpu/ozone/null_predictor.hh
index e930ca7d4..68bb7cd52 100644
--- a/src/cpu/ozone/null_predictor.hh
+++ b/src/cpu/ozone/null_predictor.hh
@@ -31,8 +31,8 @@
 #ifndef __CPU_OZONE_NULL_PREDICTOR_HH__
 #define __CPU_OZONE_NULL_PREDICTOR_HH__
 
-#include "cpu/inst_seq.hh"
 #include "base/types.hh"
+#include "cpu/inst_seq.hh"
 
 template <class Impl>
 class NullPredictor
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index ef9f2e712..5988f0e7e 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -28,10 +28,10 @@
  * Authors: Steve Reinhardt
  */
 
-#include "arch/utility.hh"
 #include "arch/faults.hh"
-#include "base/cprintf.hh"
+#include "arch/utility.hh"
 #include "base/cp_annotate.hh"
+#include "base/cprintf.hh"
 #include "base/inifile.hh"
 #include "base/loader/symtab.hh"
 #include "base/misc.hh"
@@ -39,6 +39,7 @@
 #include "base/range.hh"
 #include "base/stats/events.hh"
 #include "base/trace.hh"
+#include "base/types.hh"
 #include "cpu/base.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/profile.hh"
@@ -49,9 +50,9 @@
 #include "cpu/thread_context.hh"
 #include "mem/packet.hh"
 #include "mem/request.hh"
+#include "params/BaseSimpleCPU.hh"
 #include "sim/byteswap.hh"
 #include "sim/debug.hh"
-#include "base/types.hh"
 #include "sim/sim_events.hh"
 #include "sim/sim_object.hh"
 #include "sim/stats.hh"
@@ -67,8 +68,6 @@
 #include "mem/mem_object.hh"
 #endif // FULL_SYSTEM
 
-#include "params/BaseSimpleCPU.hh"
-
 using namespace std;
 using namespace TheISA;
 
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 7348a8576..35f74a67e 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -35,13 +35,13 @@
 #include "arch/isa_traits.hh"
 #include "arch/regfile.hh"
 #include "arch/tlb.hh"
+#include "base/types.hh"
 #include "config/full_system.hh"
 #include "cpu/thread_context.hh"
 #include "cpu/thread_state.hh"
 #include "mem/request.hh"
 #include "sim/byteswap.hh"
 #include "sim/eventq.hh"
-#include "base/types.hh"
 #include "sim/serialize.hh"
 
 class BaseCPU;
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index 58a6b7986..b1298e0e9 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -36,14 +36,14 @@
 
 #include "arch/isa_traits.hh"
 #include "arch/utility.hh"
-#include "sim/faults.hh"
 #include "base/bitfield.hh"
 #include "base/hashmap.hh"
 #include "base/misc.hh"
 #include "base/refcnt.hh"
+#include "base/types.hh"
 #include "cpu/op_class.hh"
 #include "sim/faults.hh"
-#include "base/types.hh"
+#include "sim/faults.hh"
 
 // forward declarations
 struct AlphaSimpleImpl;
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 08b9b6e0c..51ca3cca6 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -33,12 +33,12 @@
 
 #include "arch/regfile.hh"
 #include "arch/types.hh"
+#include "base/types.hh"
 #include "config/full_system.hh"
 #include "mem/request.hh"
+#include "sim/byteswap.hh"
 #include "sim/faults.hh"
-#include "base/types.hh"
 #include "sim/serialize.hh"
-#include "sim/byteswap.hh"
 
 // @todo: Figure out a more architecture independent way to obtain the ITB and
 // DTB pointers.