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authorGabe Black <gblack@eecs.umich.edu>2006-12-18 18:18:37 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-12-18 18:18:37 -0500
commitdfafe6741f9865a996488236421d57ea1e6ba815 (patch)
tree9e45e241f1ba1af540584eb128ff96c7db5f67c7 /src/cpu
parentaf1e8d2d40183549da1b982ae6e994311a77fd6a (diff)
downloadgem5-dfafe6741f9865a996488236421d57ea1e6ba815.tar.xz
Make sure you only handle branch delay slots specially when there actually was a branch.
--HG-- extra : convert_revision : ea6d33b1b9c2ba5c24225af4b10a9bd25558f1dd
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/o3/commit_impl.hh7
1 files changed, 6 insertions, 1 deletions
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 194138efc..07aadbfb0 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -731,9 +731,14 @@ DefaultCommit<Impl>::commit()
#if ISA_HAS_DELAY_SLOT
InstSeqNum bdelay_done_seq_num = squashed_inst;
bool squash_bdelay_slot = fromIEW->squashDelaySlot[tid];
+ bool branchMispredict = fromIEW->branchMispredict[tid];
- if (!squash_bdelay_slot)
+ // Squashing/not squashing the branch delay slot only makes
+ // sense when you're squashing from a branch, ie from a branch
+ // mispredict.
+ if (branchMispredict && !squash_bdelay_slot) {
bdelay_done_seq_num++;
+ }
#endif
if (fromIEW->includeSquashInst[tid] == true) {