the way i understand it, interrupts in m5 is a little bloated. the usage of CPU->checkInterrupts bool is inconsistent, and i think should eventually be phased out. For now, I've just assumed that CPU->checkInterrupts() is the way to fast path a CPU if you have no interrupts by having a simple bitfield in each ISA to determine whether interrupts are pending. getInterrupts has been mostly filled in.

src/arch/sparc/interrupts.hh:
    fill in how we do interrupts on sparc a little bit.

    1) create a bitfield for interrupts, and check that in checkInterrupts() to fast path CPU.
    2) fill in getInterrupts() a little bit.

    also, update the bitfield access to be HPSTATE::hpriv, etc.
src/arch/sparc/ua2005.cc:
    1) update formatting
    2) change the way interrupts are done to use the new way to tickle the CPU.
src/cpu/base.cc:
src/cpu/base.hh:
    overload the post_interrupt function for SPARC interrupts - which are only denoted by a single int value.

--HG--
extra : convert_revision : 9074a003eff37a40dcce78f56d20f6cbcc453eb5

2 files changed, 7 insertions, 0 deletions

diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 31604ad58..b03bc19a5 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -363,6 +363,12 @@ BaseCPU::ProfileEvent::process()
 }
 
 void
+BaseCPU::post_interrupt(int int_type)
+{
+    interrupts.post(int_type);
+}
+
+void
 BaseCPU::post_interrupt(int int_num, int index)
 {
     checkInterrupts = true;
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 8c6b079da..89c7d9dda 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -102,6 +102,7 @@ class BaseCPU : public MemObject
     TheISA::Interrupts interrupts;
 
   public:
+    virtual void post_interrupt(int int_type);
     virtual void post_interrupt(int int_num, int index);
     virtual void clear_interrupt(int int_num, int index);
     virtual void clear_interrupts();