Registers: Move the PCs out of the ISAs and into the CPUs.

4 files changed, 50 insertions, 23 deletions

diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index d88e02ff1..2edaf8f55 100644
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -63,8 +63,8 @@ using namespace std;
 SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
                            TheISA::TLB *_itb, TheISA::TLB *_dtb,
                            bool use_kernel_stats)
-    : ThreadState(_cpu, _thread_num), cpu(_cpu), system(_sys), itb(_itb),
-      dtb(_dtb)
+    : ThreadState(_cpu, _thread_num),
+      cpu(_cpu), system(_sys), itb(_itb), dtb(_dtb)
 
 {
     tc = new ProxyThreadContext<SimpleThread>(this);
@@ -194,6 +194,11 @@ SimpleThread::serialize(ostream &os)
     regs.serialize(cpu, os);
     SERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs);
     SERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs);
+    SERIALIZE_SCALAR(microPC);
+    SERIALIZE_SCALAR(nextMicroPC);
+    SERIALIZE_SCALAR(PC);
+    SERIALIZE_SCALAR(nextPC);
+    SERIALIZE_SCALAR(nextNPC);
     // thread_num and cpu_id are deterministic from the config
 }
 
@@ -205,6 +210,11 @@ SimpleThread::unserialize(Checkpoint *cp, const std::string &section)
     regs.unserialize(cpu, cp, section);
     UNSERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs);
     UNSERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs);
+    UNSERIALIZE_SCALAR(microPC);
+    UNSERIALIZE_SCALAR(nextMicroPC);
+    UNSERIALIZE_SCALAR(PC);
+    UNSERIALIZE_SCALAR(nextPC);
+    UNSERIALIZE_SCALAR(nextNPC);
     // thread_num and cpu_id are deterministic from the config
 }
 
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 35a28dbb6..31e69bafe 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -107,6 +107,28 @@ class SimpleThread : public ThreadState
     TheISA::IntReg intRegs[TheISA::NumIntRegs];
     TheISA::ISA isa;    // one "instance" of the current ISA.
 
+    /** The current microcode pc for the currently executing macro
+     * operation.
+     */
+    MicroPC microPC;
+
+    /** The next microcode pc for the currently executing macro
+     * operation.
+     */
+    MicroPC nextMicroPC;
+
+    /** The current pc.
+     */
+    Addr PC;
+
+    /** The next pc.
+     */
+    Addr nextPC;
+
+    /** The next next pc.
+     */
+    Addr nextNPC;
+
   public:
     // pointer to CPU associated with this SimpleThread
     BaseCPU *cpu;
@@ -232,6 +254,9 @@ class SimpleThread : public ThreadState
     void clearArchRegs()
     {
         regs.clear();
+        microPC = 0;
+        nextMicroPC = 1;
+        PC = nextPC = nextNPC = 0;
         memset(intRegs, 0, sizeof(intRegs));
         memset(floatRegs.i, 0, sizeof(floatRegs.i));
     }
@@ -283,12 +308,12 @@ class SimpleThread : public ThreadState
 
     uint64_t readPC()
     {
-        return regs.readPC();
+        return PC;
     }
 
     void setPC(uint64_t val)
     {
-        regs.setPC(val);
+        PC = val;
     }
 
     uint64_t readMicroPC()
@@ -303,12 +328,12 @@ class SimpleThread : public ThreadState
 
     uint64_t readNextPC()
     {
-        return regs.readNextPC();
+        return nextPC;
     }
 
     void setNextPC(uint64_t val)
     {
-        regs.setNextPC(val);
+        nextPC = val;
     }
 
     uint64_t readNextMicroPC()
@@ -323,12 +348,18 @@ class SimpleThread : public ThreadState
 
     uint64_t readNextNPC()
     {
-        return regs.readNextNPC();
+#if ISA_HAS_DELAY_SLOT
+        return nextNPC;
+#else
+        return nextPC + sizeof(TheISA::MachInst);
+#endif
     }
 
     void setNextNPC(uint64_t val)
     {
-        regs.setNextNPC(val);
+#if ISA_HAS_DELAY_SLOT
+        nextNPC = val;
+#endif
     }
 
     MiscReg
diff --git a/src/cpu/thread_state.cc b/src/cpu/thread_state.cc
index d9d83fb00..53a56d9a6 100644
--- a/src/cpu/thread_state.cc
+++ b/src/cpu/thread_state.cc
@@ -56,7 +56,7 @@ ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid,
 #else
       port(NULL), process(_process), asid(_asid),
 #endif
-      microPC(0), nextMicroPC(1), funcExeInst(0), storeCondFailures(0)
+      funcExeInst(0), storeCondFailures(0)
 {
 }
 
@@ -77,8 +77,6 @@ ThreadState::serialize(std::ostream &os)
     // thread_num and cpu_id are deterministic from the config
     SERIALIZE_SCALAR(funcExeInst);
     SERIALIZE_SCALAR(inst);
-    SERIALIZE_SCALAR(microPC);
-    SERIALIZE_SCALAR(nextMicroPC);
 
 #if FULL_SYSTEM
     Tick quiesceEndTick = 0;
@@ -98,8 +96,6 @@ ThreadState::unserialize(Checkpoint *cp, const std::string &section)
     // thread_num and cpu_id are deterministic from the config
     UNSERIALIZE_SCALAR(funcExeInst);
     UNSERIALIZE_SCALAR(inst);
-    UNSERIALIZE_SCALAR(microPC);
-    UNSERIALIZE_SCALAR(nextMicroPC);
 
 #if FULL_SYSTEM
     Tick quiesceEndTick;
diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh
index 525ecca86..ba61f431d 100644
--- a/src/cpu/thread_state.hh
+++ b/src/cpu/thread_state.hh
@@ -218,16 +218,6 @@ struct ThreadState {
      */
     TheISA::MachInst inst;
 
-    /** The current microcode pc for the currently executing macro
-     * operation.
-     */
-    MicroPC microPC;
-
-    /** The next microcode pc for the currently executing macro
-     * operation.
-     */
-    MicroPC nextMicroPC;
-
   public:
     /**
      * Temporary storage to pass the source address from copy_load to